PCA9527 2 3-channel bidirectional bus extender for HDMI, I C-bus and SMBus Rev. 1.1 20 August 2021 Product data sheet 1 General description The PCA9527 is a 3-channel bidirectional open-drain bus buffer for Display Data Control (DDC) clock, data and Consumer Electronic Control (CEC) for HDMI application. The device has two power supply pins to allow voltage level shift from 2.7 V to 5 V, and a rise time accelerator on port A of each DDC clock and data for driving longer cable (up to 18 meters or 1400 pF reliably without violating the bus rise time). The 5 V tolerant CEC channel is internally connected to V and has no rise time accelerator. The CEC CC(B) channel can be used as an interrupt or reset. 2 While retaining all the operating modes and features of the I C-bus system during the 2 level shift, it also permits extension of the I C-bus by providing bidirectional buffering for data (SDA), clock (SCL), and CEC. Using the PCA9527 enables the system designer to isolate bus capacitance to meet HDMI DDC version 1.3 distance specification. The SDAx and SCLx pins are overvoltage tolerant and are high-impedance when the PCA9527 is unpowered. The port B drivers (SDAB, SCLB, CECB) with static level offset behave much like the drivers on the PCA9515 device, while the SDAA and SCLA drivers integrate the rise time accelerator, sink more current and eliminate the static offset voltage. The CECA driver has the same current and static offset voltage features as the SDAA and SCLA, but it does not have the rise time accelerator and is powered and referenced to V . This results in a LOW on the port B translating into a nearly CC(B) 0 V LOW on port A, providing zero offset. The static level offset design of the port B I/O drivers prevent them from being connected to another device that has rise time accelerator including the PCA9507 (port B), PCA9510, PCA9511, PCA9512, PCA9513, PCA9514, PCA9515, PCA9516A, PCA9517 (port B), or PCA9518A. Port A of two or more PCA9527s can be connected together, however, to allow a star topography with port A on the common bus, and port A can be connected directly to any other buffer with static or dynamic offset voltage. Multiple PCA9527s can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays to consider. Rise time accelerators on the SDAA and SCLA pins are turned on when input threshold is above 0.3V . The PCA9527 SDA and SCL drivers are not enabled unless V and CC(A) CC(A) V are above 2.7 V. The EN pin can also be used to turn the drivers on and off under CC(B) system control. Caution should be observed to only change the state of the enable pin when the bus is idle. The output pull-down on the port B internal buffer LOW is set for approximately 0.5 V, while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. 2 Features 3-channel, bidirectional buffer isolates capacitance allowing 1400 pF on port A and 400 pF on port B Exceeds 18 meters (above the maximum distance for HDMI DDC) Rise time accelerator and normal I/O on port A (no accelerator for CEC)NXP Semiconductors PCA9527 2 3-channel bidirectional bus extender for HDMI, I C-bus and SMBus Static level offset on port B Voltage level translation from 2.7 V to 5.5 V CEC is 5 V tolerant, powered by V CC(B) Upgrade replacement over PCA9507 and PCA9517A for cable application 2 I C-bus, SMBus and DDC-bus compatible Active HIGH buffer enable input Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater 2 Accommodates Standard-mode and Fast-mode I C-bus devices and multiple controllers 2 Powered-off high-impedance I C-bus pins Port A operating supply voltage range of 2.7 V to 5.5 V Port B operating supply voltage range of 2.7 V to 3.6 V 2 5 V tolerant I C-bus and enable pins 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater) ESD protection exceeds 8000 V HBM per JESD22-A114, 500 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Package offered: TSSOP10 3 Ordering information Table 1.Ordering information Type number Topside Package mark Name Description Version 1 PCA9527DP 9527 SOT552-1 TSSOP10 plastic thin shrink small outline package 10 leads body width 3 mm 1 Also known as MSOP10. Standard packing quantities and other packaging data are available at www.nxp.com/ packages/. 3.1 Ordering options Table 2.Ordering options Type number Orderable part Package Packing method Minimum Temperature number order quantity 1 PCA9527DP PCA9527DP, 118 TSSOP10 REEL 13 Q1/T1 2500 T = -40 C to +85 C amb *STANDARD MARK SMD PCA9527DPZ TSSOP10 REEL 13 Q1/T1 2500 T = -40 C to +85 C amb *STANDARD MARK SMD 2 SSB 1 Discontinued in 202104010DN - drop in replacement is PCA9527DPZ - this is documented in PCN202104008A. 2 This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in the sealed bag between uses. PCA9527 All information provided in this document is subject to legal disclaimers. NXP B.V. 2021. All rights reserved. Product data sheet Rev. 1.1 20 August 2021 2 / 23