Freescale Semiconductor Document Number: MC9S08SC4 Rev. 4, 6/2010 Data Sheet: Technical Data MC9S08SC4 8-Bit MC9S08SC4 Microcontroller Data Sheet 948F-01 Breakpoint capability to allow single breakpoint setting 8-Bit HCS08 Central Processor Unit (CPU) during in-circuit debugging Up to 40 MHz HCS08 CPU (central processor unit) up to 20 MHz bus frequency Peripherals HC08 instruction set with added BGND instruction SCI Serial Communication Interface Full-duplex non-return to zero (NRZ) On-Chip Memory 4 KB of FLASH with read/program/erase over full LIN master extended break generation operating voltage and temperature LIN slave extended break detection 256 bytes of Random-access memory (RAM) Wake-up on active edge TPMx Two 2-channel Timer/PWM modules (TPM1 Power-Saving Modes and TPM2) Two very low power stop modes 16-bit modulus or up/down counters Reduced power wait mode Input capture, output compare, buffered Clock Source Options edge-aligned or center-aligned PWM Oscillator (XOSC) Loop-control Pierce oscillator ADC Analog to Digital Converter Crystal or ceramic resonator range of 32 kHz to 38.4 kHz 8-channel, 10-bit resolution or 1 MHz to 16 MHz 2.5 s conversion time Internal Clock Source (ICS) Internal clock source Automatic compare function module containing a frequency-locked loop (FLL) controlled by internal or external reference precision Temperature sensor trimming of internal reference allows 0.2 % resolution Internal bandgap reference channel and 2.0 % deviation over temperature and voltage Input/Output supports bus frequencies from 2 MHz to 20 MHz. 12 general purpose I/O pins (GPIOs) System Protection 8 interrupt pins with selectable polarity Watchdog computer operating properly (COP) reset with Hysteresis and configurable pull-up device on all input option to run from dedicated 1 kHz internal clock source pins Configurable slew rate and drive strength on all or bus clock output pins. Low-voltage detection with reset or interrupt selectable Package Options trip points 16-TSSOP Illegal opcode detection with reset Illegal address detection with reset Operating Parameters FLASH block protect 4.5-5.5 V operation Reset on loss of clock C,V, M temperature ranges available, covering -40 - 125 C operation Development Support Single-wire background debug interface Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. Freescale Semiconductor, Inc., 2009-2010. All rights reserved.Table of Contents Chapter 1 3.9 Internal Clock Source (ICS) Characteristics 18 Device Overview 3 3.10 ADC Characteristics 19 1.1 MCU Block Diagram 3 3.11 AC Characteristics 21 Chapter 2 3.11.1 Control Timing . 21 Pins and Connections 5 3.11.2 TPM Module Timing . 22 2.1 Device Pin Assignment 5 3.12 Flash Specifications . 23 Chapter 3 3.13 EMC Performance 24 Electrical Characteristics .7 3.13.1 Radiated Emissions . 24 3.1 Introduction .7 Chapter 4 3.2 Parameter Classification .7 Ordering Information and Mechanical Drawings 25 3.3 Absolute Maximum Ratings 7 4.1 Ordering Information 25 3.4 Thermal Characteristics .8 4.1.1 Device Numbering Scheme . 25 3.5 ESD Protection and Latch-Up Immunity .9 4.2 Package Information 25 3.6 DC Characteristics 10 4.3 Mechanical Drawings 25 3.7 Supply Current Characteristics .13 Chapter 5 3.8 External Oscillator (XOSC) Characteristics .16 Revision History 29 MC9S08SC4 MCU Series Data Sheet, Rev. 4 2 Freescale Semiconductor