Document Number SAC57D54H NXP Semiconductors Rev. 7, 05/2017 Data Sheet: Technical Data SAC57D54H SAC57D54H Features Debug functionality Run-time debug control of cores and visibility of ARM Cortex-A5, 32-bit CPU system resources using the Debug Access Port Supports ARMv7- ISA (DAP) 32 KB Instruction cache, 32 KB Data cache IEEE 1149.1/ IEEE 1149.7 System JTAG Controller NEON SIMD Media Processing Engine (SJTAG) FPU supporting double precision floating point Program and Data Trace support (16-bit data width) operations implemented by the ARM Trace Port Interface Unit Memory Management Unit (TPIU) Trace capture GIC Interrupt Controller Up to 320 MHz Timer Four 8-channel Flextimer modules (FTM) ARM Cortex-M4, 32-bit CPU Two 4 channel System Timer Module (STM) Supports ARMv7 - ISA Three Software WatchDog Timers (SWT) 16 KB Instruction cache, 16 KB Data cache One 8 channel Periodic Interrupt Timer (PIT) 64 KB Tightly-Coupled Memory (TCM) Autonomous Real Time Counter (RTC) Single Precision FPU NVIC Interrupts Controller Analog 1.25 DMIPS per MHz integer performance 1 x 24 channel, 12-bit analog-to-digital converter Up to 160 MHz (ADC) 2 analog comparators (CMP) I/O Processor ARM Cortex-M0+, 32-bit CPU Security Intelligent Stepper Motor Drive Cryptographic Services Engine (CSE) Memory subsystem Safety System Memory Protection Unit ISO26262 ASIL-B compliance 4 MB on-chip flash supported with the flash Password and Device Security (PASS) supporting controller advanced censorship and life-cycle management 1 MB on-chip SRAM with ECC One Fault Collection and Control Unit (FCCU) to 1.3 MB on-chip Graphics SRAM with FlexECC collect faults and issue interrupts Supports wake-up from low power modes via the Multiple operating modes WKPU controller Includes enhanced low power operation On-chip voltage regulator Memory interfaces External 3.3 V input supply 2 x Dual QuadSPI Serial flash controllers Option for direct, external supply of core voltage Supports SDR and DDR serial flash Low Voltage Detect (LVD) and High Voltage Support for 3.3 V Hyperflash (Spansion) Detect (HVD) on various supplies and regulators DRAM controller supporting SDR and DDR2 Clock interfaces 8-40 MHz external crystal (FXOSC) 16 MHz IRC (FIRC) 128 kHz IRC (SIRC) 32 kHz external crystal (SXOSC) Clock Monitor Unit (CMU) Frequency modulated phase-locked loop (FMPLL) Real Time Counter (RTC) NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. Graphics interfaces Vivante GC355 GPU supporting OpenVG 1.1 2 x 2D-ACE Display Controllers (with inline Head-Up-Display warping) Digital RGB, TCON 0 (RSDS), TCON 1 and OpenLDI/LVDS output options Digital Video Input (VIU4) RLE Decoder for memory-memory decompression 40x4 segment LCD driver, reconfigurable as 38x6 or 36x8 Cluster peripherals Sound Generator Module (SGM) 6 Stepper Motor Drivers with Stepper Stall Detect Communication Ethernet 10/100 + AVB (ENET) MLB50 FlexCAN x 3 DSPI x 5 LINFlexD x 3 (1 x Master/Slave, 2 x Master only) I2C x 2 eDMA controller with multiple transfer request sources using DMAMUX Boot Assist Flash (BAF) supports internal flash programming SAC57D54H, Rev. 7, 05/2017 2 NXP Semiconductors