SC18IS600IBS,157 NXP

SC18IS600 2 SPI to I C-bus interface Rev. 6 4 May 2012 Product data sheet 1. General description The SC18IS600 is designed to serve as an interface between the standard SPI of a host 2 (microcontroller, microprocessor, chip set, etc.) and the serial I C-bus. This allows the 2 host to communicate directly with other I C-bus devices. The SC18IS600 can operate as 2 2 an I C-bus master-transmitter or master-receiver. The SC18IS600 controls all the I C-bus specific sequences, protocol, arbitration and timing. 2. Features and benefits SPI slave interface SPI Mode 3 2 Single master I C-bus controller Four General Purpose Input/Output (GPIO) pins Two quasi-bidirectional I/O pins 5 V tolerant I/O pins High-speed SPI: Up to 1.2 Mbit/s 2 High-speed I C-bus: 400 kbit/s 96-byte transmit buffer 96-byte receive buffer 2.4 V to 3.6 V operation Power-down mode with WAKEUP pin Internal oscillator Active LOW interrupt output Available in very small TSSOP16 and HVQFN24 packages 3. Ordering information Table 1. Ordering information Type number Package Name Description Version SC18IS600IPW TSSOP16 plastic thin shrink small outline package 16 leads body width 4.4 mm SOT403-1 SC18IS600IBS HVQFN24 plastic thermal enhanced very thin quad flat package no leads 24 terminals SOT616-3 body 4 4 0.85 mmSC18IS600 NXP Semiconductors 2 SPI to I C-bus interface 4. Block diagram SC18IS600 CONTROL RESET LOGIC MISO SDA 2 MOSI I C-BUS SPI BUFFER SCLK CONTROLLER SCL CS GPIO0 GPIO1 INT INTERRUPT GENERAL GPIO2 CONTROL PURPOSE LOGIC GPIO3 I/Os IO5 IO4/WAKEUP OSCILLATOR ON-CHIP RC OSCILLATOR 002aab712 Fig 1. Block diagram of SC18IS600 SC18IS600 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 6 4 May 2012 2 of 29 INTERCONNECT BUS LINES AND CONTROL SIGNALS