TDA19977A TDA19977B Triple input HDMI 1.3a compliant receiver interface with equalizer (up to 1080p for HDTV, and UXGA for PC formats) Rev. 02 11 May 2010 Product data sheet 1. General description The TDA19977A TDA19977B is a three input HDMI 1.3a compliant receiver with embedded EDID memory. The built-in auto-adaptive equalizer, improves signal quality and allows the use of cable lengths of up to 25 m which are laboratory tested with a 0.5 mm (24 AWG) cable at 2.05 gigasamples per second. The HDCP (TDA19977A only) key set is stored in non-volatile OTP (One Time Programmable) memory for maximum security. In addition, the TDA19977A TDA19977B is delivered with software drivers to ease configuration and use. The TDA19977A TDA19977B supports: TV resolutions: 480i (1440 480i at 60 Hz), 576i (1440 576i at 50 Hz) to HDTV (up to 1920 1080p at 50/60 Hz) WUXGA (1920 1200p at 60 Hz) reduced blanking format PC resolutions: VGA (640 480p at 60 Hz) to UXGA (1600 1200p at 60 Hz) Deep Color mode in 10-bit and 12-bit (up to 205 MHz TMDS clock) Gamut boundary description IEC 60958/IEC 61937, OBA (One Bit Audio), DST (Direct Stream Transfer) and HBR (High Bit Rate) stream The TDA19977A TDA19977B includes: An enhanced PC and TV format recognition system Generation of a 128/256/512 f system clock allowing the use of simple audio DACs s without an integrated PLL (such as the UDA1334BTS) An embedded oscillator (an external crystal can also be used) Improved audio clock generation using an external reference clock OBA (as used in SACD), DST and HBR stream support The TDA19977A TDA19977B converts HDMI streams with or without HDCP (TDA19977A only) into RGB or YCbCr digital signals. The YCbCr digital output signal can be 4:4:4 or 4:2:2 semi-planar format based on the ITU-R BT.601 standard or 4:2:2 based on the ITU-R BT.656 format. The device can adjust the output timing of the video port by altering the values of t and t . In addition, all settings are controllable using the su(Q) h(Q) 2 I C-bus.TDA19977A TDA19977B NXP Semiconductors Triple input HDMI receiver interface with digital processing 2. Features and benefits Complies with the HDMI 1.3a, DVI 1.0, CEA-861-D and HDCP (TDA19977A only) 1.2 standards Three independent HDMI inputs, up to the HDMI frequency of 205 MHz Embedded auto-adaptive equalizer on all HDMI links EDID memory: 253 shared bytes and three bytes dedicated to each HDMI input Supports color depth processing (8-bit, 10-bit or 12-bit per color) 2 Color gamut metadata packet with interrupt on each update, readable via the I C-bus 2 Up to four S/PDIF or I S-bus outputs (eight channels) at a sampling rate up to 192 kHz with IEC 60958/IEC 61937 stream 2 HBR audio stream up to 768 kHz with four demultiplexed S/PDIF or I S-bus outputs HBR streams (e.g. DTS-HD master audio and Dolby TrueHD up to eight channels due to HBR packet for stream with a frame rate up to 768 kHz) support DSD and DST audio stream up to six DSD channels output for SACD with DST audio packet support Channel status decoder supports multi-channel reception Improved audio clock generation using an external reference clock System/master clock output (128/256/512 f ) enables the use of the UDA1334BTS s The HDMI interface supports: All HDTV formats up to 1920 1080p at 50/60 Hz and WUXGA (1920 1200p at 60 Hz) with support for reduced blanking PC formats up to UXGA (1600 1200p at 60 Hz) Embedded oscillator (an external crystal can be used) Frame and field detection for interlaced video signal Sync timing measurements for format recognition Improved system for measurements of blanking and video active area allowing an accurate recognition of PC and TV formats HDCP (TDA19977A only) with repeater capability Embedded non-volatile memory storage of HDCP (TDA19977A only) keys Programmable color space input signal conversion from RGB-to-YCbCr or YCbCr-to-RGB Output formats: RGB 4:4:4, YCbCr 4:4:4, YCbCr 4:2:2 semi-planar based on the ITU-R BT.601 standard and YCbCr 4:2:2 ITU-R BT.656 2 8-bit, 10-bit or 12-bit output formats selectable using the I C-bus (8-bit and 10-bit only in 4:4:4 format) 2 I C-bus adjustable timing of video port (t and t ) su(Q) h(Q) Downsampling-by-two with selectable filters on Cb and Cr channels in 4:2:2 mode Internal video and audio pattern generator 2 Controllable using the I C-bus 5 V tolerant and bit rate up to 400 kbit/s DDC-bus inputs 5 V tolerant and bit rate up to 400 kbit/s LV-TTL outputs Power-down mode CMOS process 1.8 V and 3.3 V power supplies Lead-free (Pb) HLQFP144 package TDA19977A TDA19977B 2 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 11 May 2010 2 of 40