74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs December 2007 74ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs Features General Description Bidirectional non-inverting buffers The ABT245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus- A and B output sink capability of 64mA, source oriented applications. Current sinking capability is 64 mA capability of 32mA on both the A and B ports. The Transmit/Receive (T/R) Guaranteed output skew input determines the direction of data flow through the Guaranteed multiple output switching specifications bidirectional transceiver. Transmit (active HIGH) enables Output switching specified for both 50pF and 250pF data from A Ports to B Ports Receive (active LOW) loads enables data from B Ports to A Ports. The Output Enable Guaranteed simultaneous switching, noise level and input, when HIGH, disables both A and B ports by plac- dynamic threshold performance ing them in a HIGH Z condition. Guaranteed latchup protection High-impedance, glitch-free bus loading during entire power up and power down cycle Nondestructive, hot-insertion capability Disable time is less than enable time to avoid bus contention Ordering Information Package Order Number Number Package Description 74ABT245CSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ABT245CSJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74ABT245CMSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74ABT245CMTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1991 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ABT245 Rev. 1.5.074ABT245 Octal Bi-Directional Transceiver with 3-STATE Outputs Connection Diagram Logic Symbol Truth Table Inputs OE T/R Output L L Bus B Data to Bus A L H Bus A Data to Bus B Pin Descriptions H X HIGH Z State Pin Names Description H = HIGH Voltage Level L = LOW Voltage Level OE Output Enable Input (Active LOW) X = Immaterial T/R Transmit/Receive Input A A Side A Inputs or 3-STATE Outputs 0 7 B B Side B Inputs or 3-STATE Outputs 0 7 Logic Diagram 1991 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ABT245 Rev. 1.5.0 2