74HC244 Octal 3State Noninverting Buffer/Line Driver/ Line Receiver HighPerformance SiliconGate CMOS 74HC244 PIN ASSIGNMENT LOGIC DIAGRAM 218 ENABLE A 1 20 V A1 YA1 CC A1 2 19 ENABLE B 4 16 A2 YA2 YB4 3 18 YA1 A2 4 17 B4 6 14 A3 YA3 YB3 5 16 YA2 8 12 A4 YA4 A3 6 15 B3 DATA NONINVERTING YB2 7 14 YA3 INPUTS OUTPUTS 11 9 B1 YB1 A4 8 13 B2 YB1 9 12 YA4 13 7 B2 YB2 GND 10 11 B1 15 5 B3 YB3 17 3 FUNCTION TABLE B4 YB4 Inputs Outputs Enable A, Enable B A, B YA, YB PIN 20 = V CC 1 ENABLE A OUTPUT PIN 10 = GND LLL 19 ENABLES ENABLE B LH H HX Z Z = high impedance ORDERING INFORMATION Device Package Shipping 74HC244DTR2G TSSOP20* 2500 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb Free. MAXIMUM RATINGS Symbol Parameter Value Unit This device contains protection circuitry to guard against damage V DC Supply Voltage (Referenced to GND) 0.5 to + 7.0 V CC due to high static voltages or electric V DC Input Voltage (Referenced to GND) 0.5 to V + 0.5 V in CC fields. However, precautions must be taken to avoid applications of any V DC Output Voltage (Referenced to GND) 0.5 to V + 0.5 V out CC voltage higher than maximum rated I DC Input Current, per Pin 20 mA voltages to this highimpedance cir- in cuit. For proper operation, V and in I DC Output Current, per Pin 35 mA out V should be constrained to the out I DC Supply Current, V and GND Pins 75 mA range GND (V or V ) V . in out CC CC CC Unused inputs must always be P Power Dissipation in Still Air, TSSOP Package 450 mW D tied to an appropriate logic voltage level (e.g., either GND or V ). T Storage Temperature 65 to + 150 C CC stg Unused outputs must be left open. T Lead Temperature, 1 mm from Case for 10 Seconds C L (TSSOP Package) 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating TSSOP Package: 6.1 mW/ C from 65 to 125 C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL129/D).