74LCX2244 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs with 26 Series Resistors in the Outputs October 1995 Revised May 2003 74LCX2244 Low Voltage Buffer/Line Driver with 5V Tolerant Inputs and Outputs with 26 Series Resistors in the Outputs General Description Features The LCX2244 contains eight non-inverting buffers with 5V tolerant inputs and outputs 3-STATE outputs. The device may be employed as a mem- 2.3V to 3.6V V specifications provided CC ory address driver, clock driver and bus-oriented transmit- 7.5 ns t max (V = 3.3V) 10 A I max PD CC CC ter/receiver. The LCX2244 is designed for low voltage (2.5V or 3.3V) V applications with capability of interfac- Power down high impedance inputs and outputs CC ing to a 5V signal environment. The 26 series resistors 26 -series resistors in the outputs help reduce output overshoot and undershoot. Supports live insertion/withdrawal (Note 1) The LCX2244 is fabricated with an advanced CMOS tech- 12 mA output drive (V = 3.0V) CC nology to achieve high speed operation while maintaining Implements patented noise/EMI reduction circuitry CMOS low power dissipation. Latch-up performance exceeds 500 mA ESD performance: Human body model > 2000V Machine model > 200V Leadless DQFN package Note 1: To ensure the high-impedance state during power up or down, OE should be tied to V through a pull-up resistor: the minimum value or the CC resistor is determined by the current-sourcing capability of the driver. Ordering Code: Package Order Number Package Description Number 74LCX2244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74LCX2244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LCX2244BQ MLP020B 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, (Preliminary) (Preliminary) 2.5 x 4.5mm 74LCX2244MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide 74LCX2244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. 2003 Fairchild Semiconductor Corporation DS012569 www.fairchildsemi.comLogic Symbol Pin Descriptions IEEE/IEC Pin Names Description OE , OE 3-STATE Output Enable Inputs 1 2 I I Inputs 0 7 O O Outputs 0 7 Truth Tables Inputs Outputs OE I (Pins 12, 14, 16, 18) 1 n L L L L H H H X Z Connection Diagrams Pin Assignments for Inputs Outputs SOIC, SOP, SSOP, and TSSOP OE I (Pins 3, 5, 7, 9) 2 n LH L LH H HX Z H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance Pad Assignment for DQFN (Top Through View) www.fairchildsemi.com 2 74LCX2244