74LCX543 Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs May 1995 Revised March 2001 74LCX543 Low Voltage Octal Registered Transceiver with 5V Tolerant Inputs and Outputs General Description Features The LCX543 is a non-inverting octal transceiver containing 5V tolerant inputs and outputs two sets of D-type registers for temporary storage of data 2.3V 3.6V V specifications provided CC flowing in either direction. Separate Latch Enable and Out- 7.0 ns t max (V = 3.3V), 10 A I max PD CC CC put Enable inputs are provided for each register to permit independent input and output control in either direction of Power down high impedance inputs and outputs data flow. Supports live insertion/withdrawal (Note 1) The LCX543 is designed for low voltage (2.5V or 3.3V) V CC 24 mA Output Drive (V = 3.0V) CC applications with capability of interfacing to a 5V signal Implements patented noise/EMI reduction circuitry environment. Latch-up performance exceeds 500 mA The LCX543 is fabricated with an advanced CMOS tech- ESD performance: nology to achieve high speed operation while maintaining Human body model > 2000V CMOS low power dissipation. Machine model > 200V Note 1: To ensure the high-impedance state during power up or down, OE should be tied to V through a pull-up resistor: the minimum value or the CC resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCX543WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74LCX543MSA MSA24 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 74LCX543MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Pin Descriptions Pin Names Description OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) CEAB A-to-B Enable Input (Active LOW) CEBA B-to-A Enable Input (Active LOW) LEAB A-to-B Latch Enable Input (Active LOW) LEBA B-to-A Latch Enable Input (Active LOW) A A A-to-B Data Inputs or 0 7 B-to-A 3-STATE Outputs B B B-to-A Data Inputs or 0 7 A-to-B 3-STATE Outputs 2001 Fairchild Semiconductor Corporation DS012463 www.fairchildsemi.comLogic Symbols Data I/O Control Table Inputs Latch Status Output Buffers CEAB LEAB OEAB H X X Latched High Z X H X Latched L L X Transparent XX H High Z LX L Driving IEEE/IEC H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown B-to-A flow control is the same, except using CEBA, LEBA and OEBA Functional Description The LCX543 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A A or 0 7 take data from B B , as indicated in the Data I/O Control 0 7 Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable (LEAB) input makes the A-to-B latches transparent a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Con- trol of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 74LCX543