74LVC244ADTR2G ON Semiconductor

74LVC244A Low-Voltage CMOS Octal Buffer With 5 VTolerant Inputs and Outputs (3State, NonInverting) www.onsemi.com The 74LVC244A is a high performance, noninverting octal buffer operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V I specification of 5.5 V allows 74LVC244A inputs to be safely driven TSSOP20 QFN20 QFN20 from 5 V devices. The 74LVC244A is suitable for memory address DT SUFFIX MN SUFFIX MN SUFFIX driving and all TTL level bus oriented transceiver applications. CASE 948E CASE 485AA CASE 485CB Current drive capability is 24 mA at the outputs. The Output Enable (OE) input, when HIGH, disables the output by placing them in a HIGH Z condition. MARKING DIAGRAMS Features 20 Designed for 1.2 V to 3.6 V V Operation CC LVC 5 V Tolerant Interface Capability With 5 V TTL Logic 244A ALYW Supports Live Insertion and Withdrawal I Specification Guarantees High Impedance When V = 0 V OFF CC 1 24 mA Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (10 A) 1 Substantially Reduces System Power Requirements 1 ESD Performance: LVC 244A 244A Human Body Model >2000 V ALYW ALYW Machine Model >200 V These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant QFN20 485AA QFN20 485CB A = Assembly Location L = Wafer Lot Y = Year W = Work Week = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information on page 7 of this data sheet. This document contains information on some products that are still under development. ON Semiconductor reserves the right to change or discontinue these products without notice. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: February, 2016 Rev. 1 74LVC244A/D74LVC244A 1 V 2OE 1O0 2D0 1O1 2D1 1O2 2D2 1O3 2D3 CC 1OE 20 19 18 17 16 15 14 13 12 11 2 18 1D0 1O0 4 16 1D1 1O1 6 14 1D2 1O2 1 2 3 4567 9 8 10 1OE 1D0 2O0 1D1 2O1 1D2 2O2 1D3 2O3 GND 8 12 1D3 1O3 19 12 20 11 19 2OE QFN PIN 1 10 17 3 2D0 2O0 29 15 5 Figure 1. Pinout: 20Lead (Top View) 2D1 2O1 13 7 PIN NAMES 2D2 2O2 PINS FUNCTION 11 9 nOE Output Enable Inputs 2D3 2O3 1Dn, 2Dn Data Inputs 1On, 2On 3State Outputs Figure 2. Logic Diagram TRUTH TABLE INPUTS OUTPUTS 1OE 1Dn 1On, 2On 2OE 2Dn L L L L H H H X Z H = High Voltage Level L = Low Voltage Level Z = High Impedance State X = High or Low Voltage Level and Transitions are Acceptable For I reasons, DO NOT FLOAT Inputs CC www.onsemi.com 2