74LVC540ADTR2G ON Semiconductor

74LVC540A Low-Voltage CMOS Octal Buffer Flow Through Pinout With 5 VTolerant Inputs and Outputs www.onsemi.com (3State, Inverting) MARKING The 74LVC540A is a high performance, inverting octal buffer DIAGRAMS operating from a 1.2 to 3.6 V supply. This device is similar in function to the MC74LCX240, while providing flow through architecture. 20 20 High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved 1 LVC540A switching noise performance. A V specification of 5.5 V allows AWLYYWWG I SOIC20 WB 74LVC540A inputs to be safely driven from 5 V devices. The DW SUFFIX CASE 751D 74LVC540A is suitable for memory address driving and all TTL level 1 bus oriented transceiver applications. Current drive capability is 24 mA at the outputs. The Output Enable 20 (OE1, OE2) inputs, when HIGH, disables the outputs by placing them 20 in a HIGH Z condition. LVC 1 540A Features TSSOP20 ALYW DT SUFFIX Designed for 1.2 to 3.6 V V Operation CC CASE 948E 1 5 V Tolerant Interface Capability With 5 V TTL Logic Supports Live Insertion and Withdrawal A = Assembly Location I Specification Guarantees High Impedance When V = 0 V L, WL = Wafer Lot OFF CC Y, YY = Year 24 mA Output Sink and Source Capability W, WW = Work Week Near Zero Static Supply Current in All Three Logic States (10 A) G or = PbFree Package Substantially Reduces System Power Requirements (Note: Microdot may be in either location) Latchup Performance Exceeds 250 mA ESD Performance: Human Body Model > 2000 V ORDERING INFORMATION See detailed ordering and shipping information in the package Machine Model > 200 V dimensions section on page 7 of this data sheet. These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: December, 2015 Rev. 0 74LVC540A/D74LVC540A 1 OE1 19 OE2 V OE2 O0 O1 O2 O3 O4 O5 O6 O7 2 18 CC D0 O0 20 19 18 17 16 15 14 13 12 11 3 17 D1 O1 4 16 D2 O2 5 15 D3 O3 1 2 34567 8 9 10 OE1 D0 D1 D2 D3 D4 D5 D6 D7 GND 6 14 D4 O4 Figure 1. Pinout: 20Lead (Top View) 7 13 D5 O5 8 12 PIN NAMES D6 O6 Pins Function 9 11 OEn Output Enable Inputs D7 O7 Dn Data Inputs On 3State Outputs Figure 2. Logic Diagram TRUTH TABLE Inputs Outputs OE1 OE2 Dn On L L L H L L H L X H X Z H X X Z H = High Voltage Level L = Low Voltage Level Z = High Impedance State X = High or Low Voltage Level and Transitions are Acceptable For I reasons, DO NOT FLOAT Inputs CC www.onsemi.com 2