74LVC541A Low-Voltage CMOS Octal Buffer Flow Through Pinout With 5 VTolerant Inputs and Outputs (3State, NonInverting) www.onsemi.com The 74LVC541A is a high performance, noninverting octal buffer operating from a 1.2 to 3.6 V supply. This device is similar in function to the MC74LCX244, while providing flow through architecture. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved SOIC20 WB TSSOP20 switching noise performance. A V specification of 5.5 V allows DW SUFFIX DT SUFFIX I CASE 751D CASE 948E 74LVC541A inputs to be safely driven from 5V devices. The 74LVC541A is suitable for memory address driving and all TTL level bus oriented transceiver applications. MARKING DIAGRAMS Current drive capability is 24 mA at the outputs. The Output Enable (OE1. OE2) inputs, when HIGH, disables the output by placing them 20 in a HIGH Z condition. LVC541A AWLYYWWG Features Designed for 1.2 to 3.6 V V Operation CC 1 5 V Tolerant Interface Capability With 5 V TTL Logic SOIC20 WB Supports Live Insertion and Withdrawal 20 I Specification Guarantees High Impedance When V = 0 V OFF CC 24 mA Output Sink and Source Capability LVC 541A Near Zero Static Supply Current in All Three Logic States (10 A) ALYW Substantially Reduces System Power Requirements Latchup Performance Exceeds 250 mA 1 ESD Performance: TSSOP20 Human Body Model > 2000 V A = Assembly Location Machine Model > 200 V L, WL = Wafer Lot These Devices are PbFree, Halogen Free/BFR Free and are RoHS Y, YY = Year W, WW = Work Week Compliant G or = PbFree Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: December, 2015 Rev. 0 74LVC541A/D74LVC541A 1 OE1 19 V OE2 O0 O1 O2 O3 O4 O5 O6 O7 CC OE2 2 18 20 19 18 17 16 15 14 13 12 11 D0 O0 3 17 D1 O1 4 16 D2 O2 1 2 34567 8 9 10 5 15 D3 O3 OE1 D0 D1 D2 D3 D4 D5 D6 D7 GND 6 14 D4 O4 Figure 1. Pinout: 20Lead (Top View) 7 13 D5 O5 PIN NAMES 8 12 D6 O6 Pins Function OEn Output Enable Inputs 9 11 D7 O7 Dn Data Inputs On 3State Outputs Figure 2. Logic Diagram TRUTH TABLE Inputs Outputs OE1 OE2 Dn On L L L L L L H H X H X Z H X X Z H = High Voltage Level L = Low Voltage Level Z = High Impedance State X = High or Low Voltage Level and Transitions are Acceptable, for I reasons, CC DO NOT FLOAT Inputs www.onsemi.com 2