74LVT240, 74LVTH240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
January 2008
74LVT240, 74LVTH240
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
Features General Description
Input and output interface capability to systems at The LVT240 and LVTH240 are inverting octal buffers
5V V and line drivers designed to be employed as memory
CC
address drivers, clock drivers and bus oriented transmit-
Bushold data inputs eliminate the need for external
ters or receivers which provides improved PC board
pull-up resistors to hold unused inputs (74LVTH240),
density.
also available without bushold feature (74LVT240)
Live insertion/extraction permitted
The LVTH240 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
Power Up/Down high impedance provides glitch-free
inputs.
bus loading
Outputs source/sink 32mA/+64mA
These octal buffers and line drivers are designed for low-
Functionally compatible with the 74 series 240 voltage (3.3V) V applications, but with the capability to
CC
provide a TTL interface to a 5V environment. The LVT240
Latch-up performance exceeds 500mA
and LVTH240 are fabricated with an advanced BiCMOS
ESD performance:
technology to achieve high speed operation similar to 5V
Human-body model > 2000V
ABT while maintaining low power dissipation.
Machine model > 200V
Charged-device model > 1000V
Ordering Information
Package
Order Number Number Package Description
74LVT240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVT240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVT240MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LVT240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74LVTH240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74LVTH240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74LVTH240MSA MSA20 20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
74LVTH240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVT240, 74LVTH240 Rev. 1.5.074LVT240, 74LVTH240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
Connection Diagrams Logic Symbols
IEEE/IEC
Pin Descriptions
Pin Names Description
OE , OE 3-STATE Output Enable Inputs
1 2
Truth Tables
I I Inputs
0 7
O O 3-STATE Outputs Inputs
0 7
Outputs
OE I (Pins 12, 14, 16, 18)
1 n
LL H
LH L
H X Z
Inputs
Outputs
OE I (Pins 3, 5, 7, 9)
2 n
LL H
LH L
H X Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74LVT240, 74LVTH240 Rev. 1.5.0 2