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This literature is subject to all applicable copyright laws and is not for resale in any manner.74LVT162244 74LVTH162244 Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs March 1999 Revised June 2005 74LVT162244 74LVTH162244 Low Voltage 16-Bit Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs General Description Features The LVT162244 and LVTH162244 contain sixteen non- Input and output interface capability to systems at inverting buffers with 3-STATE outputs designed to be 5V V CC employed as a memory and address driver, clock driver, or Bushold data inputs eliminate the need for external pull- bus oriented transmitter/receiver. The device is nibble con- up resistors to hold unused inputs (74LVTH162244), trolled. Individual 3-STATE control inputs can be shorted also available without bushold feature (74LVT162244). together for 8-bit or 16-bit operation. Live insertion/extraction permitted The LVT162244 and LVTH162244 are designed with Power Up/Power Down high impedance provides glitch- equivalent 25: series resistance in both the HIGH and free bus loading LOW states of the output. This design reduces line noise in Outputs include equivalent series resistance of 25: to applications such as memory address drivers, clock driv- make external termination resistors unnecessary and ers, and bus transceivers/transmitters. reduce overshoot and undershoot The LVTH162244 data inputs include bushold, eliminating Functionally compatible with the 74 series 162244 the need for external pull-up resistors to hold unused inputs. Latch-up performance exceeds 500 mA These buffers and line drivers are designed for low-voltage ESD performance: (3.3V) V applications, but with the capability to provide a CC Human-body model 2000V TTL interface to a 5V environment. The LVT162244 and Machine model 200V LVTH162244 are fabricated with an advanced BiCMOS Charged-device 1000V technology to achieve high speed operation similar to 5V Also packaged in plastic Fine-Pitch Ball Grid Array ABT while maintaining a low power dissipation. (FBGA) Ordering Code: Package Order Number Package Description Number 74LVT162244G BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) 74LVT162244MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide (Note 2) 74LVT162244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 2) 74LVTH162244G BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) 74LVTH162244MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Tube 74LVTH162244MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide Tape and Reel 74LVTH162244MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Tube 74LVTH162244MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Tape and Reel Note 1: Ordering code G indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. 2005 Fairchild Semiconductor Corporation DS012445 www.fairchildsemi.com