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It is an advanced high- Lower power dissipation: I = 4 A (Max.) at CC speed CMOS device fabricated with silicon gate CMOS T = 25C A technology and achieves the high-speed operation simi- High noise immunity: V = V = 28% V (Min.) NIH NIL CC lar to equivalent Bipolar Schottky TTL while maintaining Power down protection is provided on all inputs the CMOS low power dissipation. Low noise: V = 0.8V (Max.) OLP An input protection circuit insures that 0V to 7V can be Pin and function compatible with 74HC125 applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Package Order Number Number Package Description 74VHC125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74VHC125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC125 Rev. 1.4.0