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It Low power dissipation: I = 4A (Max.) at T = 25C CC A achieves the high-speed operation similar to equivalent High noise immunity: V = V = 28% V (Min.) NIH NIL CC Bipolar Schottky TTL while maintaining the CMOS low Power down protection is provided on all inputs power dissipation. Low noise: V = 0.8V (Max.) OLP The VHC175 is a high-speed quad D-type flip-flop. The Pin and function compatible with 74HC175 device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip- flops, independent of the Clock or D inputs, when LOW. An input protection circuit insures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Package Order Number Number Package Description 74VHC175M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74VHC175SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC175MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter X to the ordering number. Connection Diagram Pin Description Pin Names Description D D Data Inputs 0 3 CP Clock Pulse Input MR Master Reset Input Q True Outputs Q 0 3 Q Q Complement Outputs 0 3 1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC175 Rev. 1.2