CAT24AA01, CAT24AA02 2 1-Kb and 2-Kb I C CMOS Serial EEPROM Description The CAT24AA01/24AA02 are 1 Kb and 2Kb CMOS Serial EEPROM devices internally organized as 128x8/256x8 bits. CAT24AA01, CAT24AA02 Table 1. ABSOLUTE MAXIMUM RATINGS Parameters Ratings Units Storage Temperature 65 to +150 C Voltage on any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may CC undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. CC Table 2. REABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units N (Note 3) Endurance 1,000,000 Program/Erase Cycles END T Data Retention 100 Years DR 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 3. Page Mode 25C Table 3. D.C. OPERATING CHARACTERISTICS (V = 1.7 V to 5.5 V, T = 40C to 85C, unless otherwise specied.) CC A Symbol Parameter Test Conditions Min Max Units I Read Current Read, f = 400 kHz 0.5 mA CCR SCL I Write Current Write 1 mA CCW I Standby Current All I/O Pins at GND or V 1 A SB CC I I/O Pin Leakage Pin at GND or V 1 A L CC V Input Low Voltage 0.5 V x 0.3 V IL CC V Input High Voltage V x 0.7 V + 0.5 V IH CC CC V Output Low Voltage V 2.5 V, I = 3.0 mA 0.4 V OL1 CC OL V Output Low Voltage V < 2.5 V, I = 1.0 mA 0.2 V OL2 CC OL Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 1.7 V to 5.5 V, T = 40C to 85C, unless otherwise specied.) CC A Symbol Parameter Conditions Max Units C (Note 2) SDA I/O Pin Capacitance V = 0 V 8 pF IN IN C (Note 2) Input Capacitance (other pins) V = 0 V 6 pF IN IN I (Note 4) WP Input Current V < V 100 A WP IN IH V > V 1 IN IH 4. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pulldown reverts to a weak current source. CC