CAT24C128 2 EEPROM Serial 128-Kb I C Description 2 The CAT24C128 is a EEPROM Serial 128Kb I C internally organized as 16,384 words of 8 bits each. It features a 64byte page write buffer and supports both the 2 www.onsemi.com Standard (100 kHz), Fast (400 kHz) and FastPlus (1 MHz) I C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory). OnChip ECC (Error Correction Code) makes the device suitable for high reliability applications.* UDFN8 TSSOP8 Features HU4 SUFFIX Y SUFFIX 2 CASE 517AZ CASE 948AL Supports Standard, Fast and FastPlus I C Protocol 1.8 V to 5.5 V Supply Voltage Range 64Byte Page Write Buffer Hardware Write Protection for Entire Memory SOIC8 SOIC8 WIDE 2 Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs W SUFFIX X SUFFIX (SCL and SDA) CASE 751BD CASE 751BE Low Power CMOS Technology 1,000,000 Program/Erase Cycles PIN CONFIGURATION 100 Year Data Retention Industrial and Extended Temperature Range 1 A 0 V CC This Device is PbFree, Halogen Free/BFR Free and RoHS Compliant** A WP 1 SCL A 2 V CC V SDA SS SOIC (W), TSSOP (Y), UDFN (HU4) SCL For the location of Pin 1, please consult the corresponding package drawing. CAT24C128 SDA A , A , A 2 1 0 WP PIN FUNCTION Pin Name Function A , A , A Device Address Inputs 0 1 2 V SS SDA Serial Data Input/Output Figure 1. Functional Symbol SCL Serial Clock Input WP Write Protect Input ** For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques V Power Supply CC Reference Manual, SOLDERRM/D. V Ground SS The exposed pad for the TDFN/UDFN packages can be left floating or connected to Ground. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Semiconductor Components Industries, LLC, 2013 1 Publication Order Number: May, 2018 Rev. 16 CAT24C128/DCAT24C128 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Storage Temperature 65 to +150 C Voltage on Any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than 0.5 V or higher than V + 0.5 V. During transitions, the voltage on any pin may CC undershoot to no less than 1.5 V or overshoot to no more than V + 1.5 V, for periods of less than 20 ns. CC Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units N (Notes 3, 4) Endurance 1,000,000 Program / Erase Cycles END T Data Retention 100 Years DR 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 3. Page Mode, V = 5 V, 25C CC 4. The new product revision (C) uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte has to be written, 4 bytes (including the ECC bits) are reprogrammed. It is recommended to write by multiple of 4 bytes in order to benefit from the maximum number of write cycles. Table 3. D.C. OPERATING CHARACTERISTICS Mature Product (Rev B) (V = 1.8 V to 5.5 V, T = 40C to +125C, unless otherwise specified.) CC A Symbol Parameter Test Conditions Min Max Units I Read Current Read, f = 400 kHz 1 mA CCR SCL I Write Current Write, f = 400 kHz 3 mA CCW SCL I Standby Current All I/O Pins at GND or V T = 40C to +85C 1 A SB CC A T = 40C to +125C 2 A I I/O Pin Leakage Pin at GND or V T = 40C to +85C 1 A L CC A T = 40C to +125C 2 A V Input Low Voltage 0.5 V x 0.3 V IL CC V Input High Voltage V x 0.7 V + 0.5 V IH CC CC V Output Low Voltage V 2.5 V, I = 3.0 mA 0.4 V OL1 CC OL V Output Low Voltage V < 2.5 V, I = 1.0 mA 0.2 V OL2 CC OL Table 4. PIN IMPEDANCE CHARACTERISTICS Mature Product (Rev B) (V = 1.8 V to 5.5 V, T = 40C to +125C, unless otherwise specified.) CC A Symbol Parameter Conditions Max Units C (Note 5) SDA I/O Pin Capacitance V = 0 V 8 pF IN IN C (Note 5) Input Capacitance (other pins) V = 0 V 6 pF IN IN I (Note 6) WP Input Current V < V 200 A WP IN IH V > V 1 A IN IH 5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 6. When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull down is relatively strong therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pulldown reverts to a weak current source. CC www.onsemi.com 2