2 EEPROM Serial 2-Kb I C for DDR2 DIMM SPD CAT34C02 Description 2 The CAT34C02 is a EEPROM Serial 2 Kb I C, internally organized as 16 pages of 16 bytes each, for a total of 256 bytes of 8 bits www.onsemi.com each. It features a 16byte page write buffer and supports both the 2 Standard (100 kHz) as well as Fast (400 kHz) I C protocol. Write operations can be inhibited by taking the WP pin High (this protects the entire memory) or by setting an internal Write Protect flag via Software command (this protects the lower half of the memory). TSSOP8 TDFN8 In addition to Permanent Software Write Protection, the Y SUFFIX VP2 SUFFIX CAT34C02 also features JEDEC compatible Reversible Software CASE 948AL CASE 511AK Write Protection for DDR2 Serial Presence Detect (SPD) applications operating over the 1.7 V to 3.6 V supply voltage range. The CAT34C02 is fully backwards compatible with earlier DDR1 SPD applications operating over the 1.7 V to 5.5 V supply UDFN8 EP voltage range. HU4 SUFFIX Features CASE 517AZ 2 Supports Standard and Fast I C Protocol 1.7 V to 5.5 V Supply Voltage Range PIN CONFIGURATION 16Byte Page Write Buffer Hardware Write Protection for Entire Memory 1 A 0 V CC Software Write Protection for Lower 128 Bytes A WP 1 2 Schmitt Triggers and Noise Suppression Filters on I C Bus Inputs SCL A 2 (SCL and SDA) V SDA SS Low power CMOS Technology TSSOP (Y), TDFN (VP2), 1,000,000 Program/Erase Cycles UDFN (HU4) 100 Year Data Retention For the location of Pin 1, please consult the Industrial and Extended Temperature Range corresponding package drawing. This Device is PbFree, Halogen Free/BFR Free and RoHS Compliant* V CC PIN FUNCTION Pin Name Function SCL A , A , A Device Address Input 0 1 2 SDA Serial Data Input/Output CAT34C02 SDA A , A , A SCL Serial Clock Input 2 1 0 WP Write Protect Input WP V Power Supply CC V Ground SS V SS Figure 1. Functional Symbol ORDERING INFORMATION *For additional information on our PbFree strategy and soldering details, please See detailed ordering and shipping information in the package download the ON Semiconductor Soldering and Mounting Techniques dimensions section on page 10 of this data sheet. Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2012 1 Publication Order Number: August, 2021 Rev. 21 CAT34C02/DCAT34C02 Table 1. ABSOLUTE MAXIMUM RATINGS Parameter Rating Unit Operating Temperature 45 to +130 C Storage Temperature 65 to +150 C Voltage on Any Pin with Respect to Ground (Note 1) 0.5 to +6.5 V Voltage on Pin A with Respect to Ground 0.5 to +10.5 V 0 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. The DC input voltage on any pin should not be lower than 0.5 V. During transitions, the voltage on any pin may undershoot to no less than 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2) Symbol Parameter Min Units N (Note 3) Endurance 1,000,000 Program/ Erase Cycles END T Data Retention 100 Years DR 2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 3. Page Mode, V = 5 V, 25C CC Table 3. D.C. OPERATING CHARACTERISTICS (V = 1.7 V to 5.5 V, T = 40C to +85C and V = 2.5 V to 5.5 V, T = 40C to +125C, unless otherwise specified.) CC A CC A Symbol Parameter Test Conditions Min Max Units I Supply Current V < 3.6 V, f = 100 kHz 1 mA CC CC SCL V > 3.6 V, f = 400 kHz 2 CC SCL I Standby Current All I/O Pins at GND or V T = 40C to +85C 1 A SB CC A V 3.3 V CC T = 40C to +85C 3 A V > 3.3 V CC T = 40C to +125C 5 A I I/O Pin Leakage Pin at GND or V 2 A L CC V Input Low Voltage 0.5 0.3 x V V IL CC V Input High Voltage 0.7 x V V + 0.5* IH CC CC V Output Low Voltage V > 2.5 V, I = 3 mA 0.4 OL CC OL V < 2.5 V, I = 1 mA 0.2 CC OL *V Max = 4 V for SDA and SCL when V = 0 V. IH CC Table 4. PIN IMPEDANCE CHARACTERISTICS (V = 1.7 V to 5.5 V, T = 40C to +85C and V = 2.5 V to 5.5 V, T = 40C to +125C, unless otherwise specified.) CC A CC A Symbol Parameter Conditions Max Units C (Note 4) SDA I/O Pin Capacitance V = 0 V, f = 1.0 MHz, V = 5.0 V 8 pF IN IN CC Other Input Pins 6 I (Note 5) WP Input Current V < V , V = 5.5 V 130 A WP IN IH CC V < V , V = 3.6 V 120 IN IH CC V < V , V = 1.7 V 80 IN IH CC V > V 2 IN IH I (Note 5) Address Input Current V < V , V = 5.5 V 50 A A IN IH CC (A0, A1, A2) V < V , V = 3.6 V 35 IN IH CC Product Rev H V < V , V = 1.7 V 25 IN IH CC V > V 2 IN IH 4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100 and JEDEC test methods. 5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pulldown is relatively strong therefore the external driver must be able to supply the pulldown current when attempting to drive the input HIGH. To conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V ), the strong pulldown reverts to a weak current source. CC www.onsemi.com 2