CAT28C64B 64K-Bit CMOS PARALLEL EEPROM FEATURES Fast read access times: Commercial, industrial and automotive 90/120/150ns temperature ranges Low power CMOS dissipation: Automatic page write operation: Active: 25 mA max. 1 to 32 bytes in 5ms Standby: 100 A max. Page load timer Simple write operation: End of write detection: On-chip address and data latches Toggle bit Self-timed write cycle with auto-clear DATADATADATADATADATA polling Fast write cycle time: 100,000 program/erase cycles 5ms max. 100 year data retention CMOS and TTL compatible I/O Hardware and software write protection DESCRIPTION The CAT28C64B is manufactured using Catalysts The CAT28C64B is a fast, low power, 5V-only CMOS advanced CMOS floating gate technology. It is designed Parallel EEPROM organized as 8K x 8-bits. It requires a to endure 100,000 program/erase cycles and has a data simple interface for in-system programming. On-chip retention of 100 years. The device is available in JEDEC- address and data latches, self-timed write cycle with approved 28-pin DIP, TSOP, SOIC, or, 32-pin PLCC auto-clear and V power up/down write protection CC package . eliminate additional timing and protection hardware. DATA Polling and Toggle status bits signal the start and end of the self-timed write cycle. Additionally, the CAT28C64B features hardware and software write protection. BLOCK DIAGRAM 8,192 x 8 ROW ADDR. BUFFER A A EEPROM 5 12 DECODER & LATCHES ARRAY INADVERTENT HIGH VOLTAGE 32 BYTE PAGE V WRITE GENERATOR CC REGISTER PROTECTION CE CONTROL OE LOGIC WE I/O BUFFERS DATA POLLING AND TIMER TOGGLE BIT I/O I/O 0 7 ADDR. BUFFER A A COLUMN 0 4 & LATCHES DECODER 2009 SCILLC. All rights reserved. Doc. No. MD-1011, Rev. I 1 Characteristics subject to change without noticeCAT28C64B PIN CONFIGURATION DIP Package (P, L) SOIC Package (J, W) (K, X) NC 1 28 V CC NC 1 28 V CC A 2 27 WE 12 A 2 27 WE 12 A 3 26 NC 7 A 3 26 NC 7 A 4 25 A 6 8 A 4 25 A 6 8 A 5 24 A 5 9 A 5 24 A 5 9 A 6 23 A 4 11 A 6 23 A 4 11 A 7 22 OE 3 A 7 22 OE 3 A 8 21 A 2 10 A 8 21 A 2 10 A 9 20 CE 1 A 9 20 CE 1 A 10 19 I/O 0 7 A 10 19 I/O 0 7 I/O 11 18 I/O 0 6 I/O 11 18 I/O 0 6 I/O 12 17 I/O 1 5 I/O 12 17 I/O 1 5 I/O 13 16 I/O 2 4 I/O 13 16 I/O 2 4 V 14 15 I/O SS 3 V 14 15 I/O SS 3 TSOP Package (8mm x 13.4mm) (H13) PLCC Package (N, G) 28 OE 1 A 10 A 2 27 CE 11 4321 323130 A 3 26 I/O 9 7 5 29 A A 6 8 A 4 25 I/O 8 6 6 28 A A 24 5 9 NC 5 I/O 5 WE 6 23 I/O 7 27 A A 4 4 11 V 7 22 I/O CC 3 8 26 A NC 3 21 NC 8 GND 9 25 A TOP VIEW OE 9 20 A I/O 2 12 2 A 10 19 I/O 10 24 7 1 A A 1 10 A 11 18 I/O 6 0 11 23 A CE 0 17 A 12 A 5 0 12 22 A 13 16 NC I/O A 4 1 7 A 14 15 A 3 2 13 21 I/O I/O 0 6 14 15 16 17 18 19 20 PIN FUNCTIONS Pin Name Function Pin Name Function A A Address Inputs WE Write Enable 0 12 I/O I/O Data Inputs/Outputs V 5 V Supply 0 7 CC CE Chip Enable V Ground SS OE Output Enable NC No Connect Doc. No. MD-1011, Rev. I 2009 SCILLC. All rights reserved. 2 Characteristics subject to change without notice I/O A 1 7 I/O A 2 12 V NC SS NC NC I/O V 3 CC I/O WE 4 I/O NC 5