CAT28F001G-12T ON Semiconductor

CAT28F001 1 Megabit CMOS Boot Block Licensed Intel second source Flash Memory FEATURES Deep Powerdown Mode Fast Read Access Time: 90/120 ns 0.05 A I Typical On-Chip Address and Data Latches CC 0.8 A I Typical Blocked Architecture PP Hardware Data Protection One 8 KB Boot Block w/ Lock Out Electronic Signature Top or Bottom Locations 100,000 Program/Erase Cycles and 10 Year Two 4 KB Parameter Blocks Data Retention One 112 KB Main Block JEDEC Standard Pinouts: Low Power CMOS Operation 32 pin DIP 12.0V 5% Programming and Erase Voltage 32 pin PLCC Automated Program & Erase Algorithms 32 pin TSOP High Speed Programming Reset/Deep Power Down Mode Commercial, Industrial and Automotive Gree Package Options Available Temperature Ranges DESCRIPTION The CAT28F001 is a high speed 128K X 8 bit electrically The CAT28F001 is designed with a signature mode erasable and reprogrammable Flash memory ideally which allows the user to identify the IC manufacturer and suited for applications requiring in-system or after sale device type. The CAT28F001 is also designed with on- code updates. Chip Address Latches, Data Latches, Programming and Erase Algorithms. The CAT28F001 has a blocked architecture with one 8 KB Boot Block, two 4 KB Parameter Blocks and one 112 The CAT28F001 is manufactured using Catalysts ad- KB Main Block. The Boot Block section can be at the top vanced CMOS floating gate technology. It is designed or bottom of the memory map and includes a reprogram- to endure 100,000 program/erase cycles and has a data ming write lock out feature to guarantee data integrity. It retention of 10 years. The device is available in JEDEC is designed to contain secure code which will bring up approved 32-pin plastic DIP, PLCC or TSOP packages. the system minimally and download code to other loca- tions of CAT28F001. BLOCK DIAGRAM I/O I/O 0 7 ADDRESS COUNTER I/O BUFFERS WRITE STATE ERASE VOLTAGE MACHINE SWITCH STATUS RP REGISTER WE DATA SENSE COMMAND PROGRAM VOLTAGE CE, OE LOGIC LATCH AMP REGISTER SWITCH CE OE Y-GATING Y-DECODER A A 0 16 8K-BYTE BOOT BLOCK 4K-BYTE PARAMETER BLOCK X-DECODER 4K-BYTE PARAMETER BLOCK VOLTAGE VERIFY 112K-BYTE MAIN BLOCK SWITCH 2008 SCILLC. All rights reserved. Doc. No. MD-1078, Rev. K Characteristics subject to change without notice 1 ADDRESS LATCH COMPARATORCAT28F001 PIN CONFIGURATION PLCC Package (N, G) DIP Package (L) V 1 32 V PP CC A 2 31 WE 16 A 3 30 RP 15 4321 323130 A 4 29 A 5 29 12 14 A A 7 14 A 5 28 A 7 13 6 28 A A 6 13 A 6 27 A 6 8 7 27 A A 5 8 A 7 26 A 5 9 8 26 A A 4 9 A 8 25 A 4 11 9 25 A A 3 11 A 9 24 OE 3 10 24 A OE 2 A 10 23 A 2 10 11 23 A A 1 10 A 11 22 CE 1 12 22 A 28F001 F02CE 0 A 12 21 I/O 0 7 13 21 I/O I/O I/O 13 20 I/O 0 7 0 6 14 15 16 17 18 19 20 I/O 14 19 I/O 1 5 I/O 15 18 I/O 2 4 V 16 17 I/O SS 3 TSOP Package (Standard Pinout) (T, H) A 1 32 OE 11 A 2 31 A 9 10 A 3 30 CE 8 A 4 29 I/O 13 7 A 5 28 I/O 14 6 RP 6 27 I/O 5 WE 7 26 I/O 4 V 8 25 I/O CC 3 V 9 24 V PP SS A 10 23 I/O 16 2 A 11 22 I/O 15 1 A 12 21 I/O 12 0 A 13 20 A 7 0 A 14 19 A 6 1 A 15 18 A 5 2 A 16 17 A 4 3 PIN FUNCTIONS Pin Name Type Function A A Input Address Inputs for 0 16 memory addressing I/O I/O I/O Data Input/Output 0 7 CE Input Chip Enable OE Input Output Enable WE Input Write Enable V Voltage Supply CC V Ground SS V Program/Erase PP Voltage Supply RP Input Power Down 2008 SCILLC. All rights reserved. Doc. No. MD-1078, Rev. K 2 Characteristics subject to change without notice I/O A 1 12 I/O A 2 15 V A SS 16 I/O V 3 PP I/O V 4 CC I/O WE 5 I/O RP 6