CAT28F010GI12 ON Semiconductor

CAT28F010 Licensed Intel 1 Megabit CMOS Flash Memory second source FEATURES Commercial, industrial and automotive Fast read access time: 90/120 ns temperature ranges Low power CMOS dissipation: On-chip address and data latches Active: 30 mA max (CMOS/TTL levels) Standby: 1 mA max (TTL levels) JEDEC standard pinouts: Standby: 100 A max (CMOS levels) 32-pin DIP High speed programming: 32-pin PLCC 10 s per byte 32-pin TSOP (8 x 20) 2 Sec Typ Chip Program 100,000 program/erase cycles 0.5 seconds typical chip-erase 10 year data retention 12.0V 5% programming and erase voltage Electronic signature Stop timer for program/erase DESCRIPTION using a two write cycle scheme. Address and Data are The CAT28F010 is a high speed 128K x 8-bit electrically latched to free the I/O bus and address bus during the erasable and reprogrammable Flash memory ideally write operation. suited for applications requiring in-system or after-sale code updates. Electrical erasure of the full memory The CAT28F010 is manufactured using Catalysts contents is achieved typically within 0.5 second. advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data It is pin and Read timing compatible with standard retention of 10 years. The device is available in JEDEC EPROM and EEPROM devices. Programming and approved 32-pin plastic DIP, 32-pin PLCC or 32-pin Erase are performed through an operation and verify TSOP packages. algorithm. The instructions are input via the I/O bus, I/O I/O BLOCK DIAGRAM 0 7 I/O BUFFERS ERASE VOLTAGE SWITCH WE DATA SENSE COMMAND PROGRAM VOLTAGE CE, OE LOGIC LATCH AMP REGISTER SWITCH CE OE Y-GATING Y-DECODER 1,048,576 BIT A A 0 16 MEMORY X-DECODER ARRAY VOLTAGE VERIFY SWITCH 2009 SCILLC. All rights reserved. Doc. No. MD-1019, Rev. G Characteristics subject to change without notice 1 ADDRESS LATCHCAT28F010 PIN CONFIGURATION PIN FUNCTIONS DIP Package (L) Pin Name Type Function V 1 32 V PP CC A A Input Address Inputs for 0 16 A 2 31 WE 16 PLCC Package (N, G) memory addressing A 3 30 N/C 15 A 4 29 A 12 14 I/O I/O I/O Data Input/Output 0 7 A 5 28 A 7 13 A 6 27 A 6 8 CE Input Chip Enable 4321 323130 A 7 26 A 5 9 5 29 A A 7 14 A 8 25 A 4 11 OE Input Output Enable 6 28 A A 6 13 A 9 24 OE 3 7 27 A A 5 8 A 10 23 A WE Input Write Enable 2 10 8 26 A A 4 9 A 11 22 CE 1 A 9 25 A 3 11 V Voltage Supply CC A 12 21 I/O 0 7 10 24 A OE 2 I/O 13 20 I/O 0 6 11 23 A A 1 10 V Ground SS I/O 14 19 I/O 1 5 12 22 A CE 0 I/O 15 18 I/O 2 4 13 21 I/O I/O 0 7 V Program/Erase PP V 16 17 I/O 14 15 16 17 18 19 20 SS 3 Voltage Supply TSOP Package (Standard Pinout 8mm x 20mm) (T, H) A 1 32 OE 11 A 2 31 A 9 10 A 3 30 CE 8 A 4 29 I/O 13 7 A 5 28 I/O 14 6 NC 6 27 I/O 5 WE 7 26 I/O 4 V 8 25 I/O CC 3 V 9 24 V PP SS A 10 23 I/O 16 2 A 11 22 I/O 15 1 A 12 21 I/O 12 0 A 13 20 A 7 0 A 14 19 A 6 1 A 15 18 A 5 2 A 16 17 A 4 3 TSOP Package (Reverse Pinout) (TR, HR) OE 1 32 A 11 A 2 31 A 10 9 CE 3 30 A 8 I/O 4 29 A 7 13 I/O 5 28 A 6 14 I/O 6 27 NC 5 I/O 7 26 WE 4 I/O 8 25 V 3 CC V 9 24 V SS PP 10 23 A I/O 2 16 11 22 A I/O 1 15 12 21 A I/O 0 12 13 20 A A 0 7 14 19 A A 1 6 15 18 A A 2 5 16 17 A A 3 4 Doc. No. MD-1019, Rev. G 2009 SCILLC. All rights reserved. 2 Characteristics subject to change without notice I/O A 1 12 I/O A 2 15 V A SS 16 I/O V 3 PP I/O V 4 CC I/O WE 5 I/O N/C 6