P ESD8451, SZESD8451 ESD Protection Diodes Low Capacitance ESD Protection Diode for High Speed Data Line The ESD8451 Series ESD protection diodes are designed to protect www.onsemi.com high speed data lines from ESD. Ultralow capacitance and low ESD clamping voltage make this device an ideal solution for protecting voltage sensitive high speed data lines. MARKING DIAGRAMS Features PIN 1 Low Capacitance (0.30 pF Max, I/O to GND) X3DFN2 M Protection for the Following IEC Standards: CASE 152AF IEC 6100042 (Level 4) ISO10605 330 pF / 2 k 30 kV Contact XDFN2 A M Low ESD Clamping Voltage CASE 711AM SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements AECQ101 Qualified and PPAP Capable P, A = Specific Device Code M = Date Code These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant Typical Applications PIN CONFIGURATION USB 3.0 AND SCHEMATIC MHL 2.0 eSATA 12 MAXIMUM RATINGS (T = 25C unless otherwise noted) J Rating Symbol Value Unit Operating Junction Temperature Range T 55 to +125 C J Storage Temperature Range T 55 to +150 C stg Lead Solder Temperature T 260 C L Maximum (10 Seconds) IEC 6100042 Contact (ESD) ESD 15 kV IEC 6100042 Air (ESD) ESD 15 kV Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be ORDERING INFORMATION assumed, damage may occur and reliability may be affected. See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. See Application Note AND8308/D for further description of survivability specs. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: June, 2016 Rev. 8 ESD8451/D =ESD8451, SZESD8451 ELECTRICAL CHARACTERISTICS I (T = 25C unless otherwise noted) A I PP Symbol Parameter R DYN V Working Peak Voltage RWM I HOLD I Maximum Reverse Leakage Current V R RWM I T V V Breakdown Voltage I V V V V BR T BR C RWM HOLD I R I V V R V V BR HOLD RWM C I Test Current I T T I V Holding Reverse Voltage HOLD HOLD I Holding Reverse Current HOLD R DYN R Dynamic Resistance DYN I PP I Maximum Peak Pulse Current PP V = V + (I * R ) C HOLD PP DYN V Clamping Voltage I C PP V = V + (I * R ) C HOLD PP DYN ELECTRICAL CHARACTERISTICS (T = 25C unless otherwise specified) A Parameter Symbol Conditions Min Typ Max Unit Reverse Working Voltage V I/O Pin to GND 3.3 V RWM Breakdown Voltage V I = 1 mA, I/O Pin to GND 5.5 7.9 8.3 V BR T Reverse Leakage Current I V = 3.3 V, I/O Pin to GND 500 nA R RWM Reverse Holding Voltage V I/O Pin to GND 2.05 V HOLD Holding Reverse Current I I/O Pin to GND 17 mA HOLD Clamping Voltage (Note 1) V IEC6100042, 8 KV Contact V C ESD8451MUT5G V I = 3.7 A, 8/20 s pulse 13.7 V C PP Clamping Voltage ESD8451N2T5G V I = 5.0 A, 8/20 s pulse 17.0 V C PP Clamping Voltage ESD8451MUT5G V 11.0 V C I = 8 A IEC 6100042 Level 2 equivalent PP Clamping Voltage (4 kV Contact, 4 kV Air) TLP (Note 2) I = 16 A 19.0 PP IEC 6100042 Level 4 equivalent (8 kV Contact, 8 kV Air) ESD8451N2T5G V 9.0 V I = 8 A IEC 6100042 Level 2 equivalent C PP Clamping Voltage (4 kV Contact, 4 kV Air) TLP (Note 2) I = 16 A 16.0 PP IEC 6100042 Level 4 equivalent (8 kV Contact, 8 kV Air) ESD8451MUT5G R Pin1 to Pin2 1.0 DYN Dynamic Resistance Pin2 to Pin1 1.0 ESD8451N2T5G R Pin1 to Pin2 0.84 DYN Dynamic Resistance Pin2 to Pin1 0.84 Junction Capacitance C V = 0 V, f = 1 MHz 0.20 0.30 pF J R Junction Capacitance C V = 0 V, f = 2.5 GHz 0.19 0.25 pF J R 1. For test procedure see Figure 16 and application note AND8307/D. 2. ANSI/ESD STM5.5.1 Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model. TLP conditions: Z = 50 , t = 100 ns, t = 4 ns, averaging window t = 30 ns to t = 60 ns. 0 p r 1 2 www.onsemi.com 2