Gate Drivers, High-Speed, Low-Side, Single 9-A FAN3121, FAN3122 Description The FAN3121 and FAN3122 MOSFET drivers are designed to drive N channel enhancement MOSFETs in low side switching www.onsemi.com applications by providing high peak current pulses. The drivers are available with either TTL input thresholds (FAN312xT) or VDD proportional CMOS input thresholds (FAN312xC). Internal circuitry provides an undervoltage lockout function by holding the WDFN8 3x3, 0.65P CASE 511CD output low until the supply voltage is within the operating range. 1 FAN312x drivers incorporate the MillerDrive architecture for the final output stage. This bipolar / MOSFET combination provides the 8 SOIC8 highest peak current during the Miller plateau stage of the MOSFET CASE 751EB turnon / turnoff process. 1 The FAN3121 and FAN3122 drivers implement an enable function on pin 3 (EN), previously unused in the industrystandard pinout. MARKING DIAGRAM The pin is internally pulled up to V for active HIGH logic and can DD be left open for standard operation. 8 The commercial FAN3121/22 is available in a 3x3 mm 8lead XXXXX XXXXX thermallyenhanced MLP package or an 8lead SOIC package with XXXXX AYWW ALYW the option for an exposed pad. 1 Features WDFN8 SOIC8 IndustryStandard Pinout with Enable Input 4.5V to 18V Operating Range A = Assembly Location L = Wafer Lot 11.4 A Peak Sink at V = 12 V DD Y = Year 9.7A Sink / 7.1A Source at V = 6 V OUT W = Work Week Inverting Configuration (FAN3121) and = PbFree Package (Note: Microdot may be in either location) NonInverting Configuration (FAN3122) *This information is generic. Please refer to device Internal Resistors Turn Driver Off if No Inputs data sheet for actual part marking. 23ns / 19ns Typical Rise/Fall Times (10 nF Load) PbFree indicator, G or microdot , may or may not be present. 18 ns to 23 ns Typical Propagation Delay Time Choice of TTL or CMOS Input Thresholds MillerDrive Technology ORDERING INFORMATION See detailed ordering and shipping information on page 17 of Available in Thermally Enhanced 3x3 mm 8Lead this data sheet. MLP or 8Lead SOIC Package (PbFree Finish) Rated from 40C to +125C These are PbFree Devices Applications Synchronous Rectifier Circuits HighEfficiency MOSFET Switching SwitchMode Power Supplies DCtoDC Converters Motor Control Semiconductor Components Industries, LLC, 2019 1 Publication Order Number: July, 2020 Rev. 2 FAN3121/DFAN3121, FAN3122 PIN CONFIGURATIONS VDD VDD VDD 8 VDD 1 8 1 IN 2 7 IN 2 7 OUT OUT EN 6 3 6 EN 3 OUT OUT GND 4 5 GND GND 4 5 GND Figure 1. FAN3121 Pin Configuration Figure 2. FAN3122 Pin Configuration PACKAGE OUTLINES 1 8 1 8 2 2 7 7 3 6 3 6 4 5 4 5 Figure 3. 3x3 mm MLP8 (Top View) Figure 4. SOIC8 (Top View) THERMAL CHARACTERISTICS (Note 1) JL JT JA JB JT (Note 2) (Note 3) (Note 4) (Note 5) (Note 6) Package Unit 8Lead 3x3 mm Molded Leadless Package (MLP) 1.2 64 42 2.8 0.7 C/W 8Pin Small Outline Integrated Circuit (SOIC) 38 29 87 41 2.3 C/W 1. Estimates derived from thermal simulation actual values depend on the application. 2. Theta JL ( ): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) JL that are typically soldered to a PCB. 3. Theta JT ( ): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform JT temperature by a top side heatsink. 4. Theta JA ( ): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given JA is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD512, JESD515, and JESD517, as appropriate. 5. Psi JB ( ): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application JB circuit board reference point for the thermal environment defined in Note 4. For the MLP8 package, the board reference is defined as the PCB copper connected to the thermal pad and protruding from either end of the package. For the SOIC8 package, the board reference is defined as the PCB copper adjacent to pin 6. 6. Psi JT ( ): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of JT the top of the package for the thermal environment defined in Note 4. www.onsemi.com 2