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This literature is subject to all applicable copyright laws and is not for resale in any manner.FIN1215 / FIN1216 / FIN1217 LVDS 21-Bit Serializers / De-Serializers September 2009 FIN1215 / FIN1216 / FIN1217/ FIN1218 LVDS 21-Bit Serializers / De-Serializers Features Description The FIN1217 and FIN1215 transform 21-bit wide Low Power Consumption parallel LVTTL (Low-Voltage TTL) data into three serial 20MHz to 85MHz Shift Clock Support LVDS (Low-Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in 50% Duty Cycle on the Clock Output of Receiver parallel with the data stream over a separate LVDS link. 1V Common-mode Range ~1.2V Every cycle of transmit clock, 21 bits of input LVTTL data are sampled and transmitted. Narrow Bus Reduces Cable Size and Cost The FIN1216 and FIN1218 receives and converts the High Throughput: 1.785Gbps three serial LVDS data streams back into 21 bits of Up to 595Mbps per Channel LVTTL data. Table 1 provides a matrix summary of the serializers and de-serializers available. For the Internal PLL with No External Components FIN1217, at a transmit clock frequency of 85MHz, 21 Compatible with TIA/EIA-644 Specification bits of LVTTL data are transmitted at a rate of 595Mbps per LVDS channel. Offered in 48-lead TSSOP Packages These chipsets solve EMI and cable size problems associated with wide and high-speed TTL interfaces. Ordering Information Operating Packing Eco Part Number Temperature Package Method Status Range FIN1215MTDX FIN1216MTDX -40 to + 85C RoHS 48-Lead Thin Shrink Small Outline Package (TSSOP) Tape and Reel FIN1217MTDX FIN1218MTDX (Preliminary) For Fairchilds definition of Eco Status, please visit: