FQD12N20L / FQU12N20L January 2009 QFET FQD12N20L / FQU12N20L 200V LOGIC N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect 9.0A, 200V, R = 0.28 V = 10 V DS(on) GS transistors are produced using Fairchilds proprietary, Low gate charge ( typical 16 nC) planar stripe, DMOS technology. Low Crss ( typical 17 pF) This advanced technology has been especially tailored to Fast switching minimize on-state resistance, provide superior switching 100% avalanche tested performance, and withstand high energy pulse in the Improved dv/dt capability avalanche and commutation mode. These devices are well Low level gate drive requirement allowing direct suited for high efficiency switching DC/DC converters, opration from logic drivers switch mode power supply, motor control. RoHS Compliant D D G D-PAK I-PAK G S G FQD Series FQU Series D S S Absolute Maximum Ratings T = 25C unless otherwise noted C Symbol Parameter FQD12N20L / FQU12N20L Units V Drain-Source Voltage 200 V DSS I - Continuous (T = 25C) Drain Current 9.0 A D C - Continuous (T = 100C) 5.7 A C I (Note 1) Drain Current - Pulsed 36 A DM V Gate-Source Voltage 20 V GSS E (Note 2) Single Pulsed Avalanche Energy 210 mJ AS I Avalanche Current (Note 1) 9.0 A AR E (Note 1) Repetitive Avalanche Energy 5.5 mJ AR dv/dt Peak Diode Recovery dv/dt (Note 3) 5.5 V/ns Power Dissipation (T = 25C) * 2.5 W P A D Power Dissipation (T = 25C) 55 W C - Derate above 25C 0.44 W/C T , T Operating and Storage Temperature Range -55 to +150 C J STG Maximum lead temperature for soldering purposes, T 300 C L 1/8 from case for 5 seconds Thermal Characteristics Symbol Parameter Typ Max Units R Thermal Resistance, Junction-to-Case -- 2.27 C/W JC R Thermal Resistance, Junction-to-Ambient * -- 50 C/W JA R Thermal Resistance, Junction-to-Ambient -- 110 C/W JA * When mounted on the minimum pad size recommended (PCB Mount) 2009 Fairchild Semiconductor Corporation Rev. A2, January 2009FQD12N20L / FQU12N20L Electrical Characteristics T = 25C unless otherwise noted C Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BV V = 0 V, I = 250 A Drain-Source Breakdown Voltage 200 -- -- V DSS GS D BV Breakdown Voltage Temperature DSS I = 250 A, Referenced to 25C -- 0.14 -- V/C D / T Coefficient J I V = 200 V, V = 0 V -- -- 1 A DSS DS GS Zero Gate Voltage Drain Current V = 160 V, T = 125C -- -- 10 A DS C I Gate-Body Leakage Current, Forward V = 20 V, V = 0 V -- -- 100 nA GSSF GS DS I V = -20 V, V = 0 V Gate-Body Leakage Current, Reverse -- -- -100 nA GSSR GS DS On Characteristics V Gate Threshold Voltage V = V , I = 250 A 1.0 -- 2.0 V GS(th) DS GS D V = 10 V, I = 4.5 A R Static Drain-Source GS D 0.22 0.28 DS(on) -- On-Resistance V = 5 V, I = 4.5 A 0.25 0.32 GS D (Note 4) g V = 30 V, I = 4.5 A Forward Transconductance -- 11.6 -- S FS DS D Dynamic Characteristics C Input Capacitance -- 830 1080 pF iss V = 25 V, V = 0 V, DS GS C Output Capacitance -- 120 155 pF oss f = 1.0 MHz C Reverse Transfer Capacitance -- 17 22 pF rss Switching Characteristics t Turn-On Delay Time -- 15 40 ns d(on) V = 100 V, I = 11.6 A, DD D t Turn-On Rise Time -- 190 390 ns r R = 25 G t Turn-Off Delay Time -- 60 130 ns d(off) (Note 4, 5) t Turn-Off Fall Time -- 120 250 ns f Q Total Gate Charge -- 16 21 nC g V = 160 V, I = 11.6 A, DS D Q Gate-Source Charge -- 2.8 -- nC gs V = 5 V GS (Note 4, 5) Q Gate-Drain Charge -- 7.6 -- nC gd Drain-Source Diode Characteristics and Maximum Ratings I Maximum Continuous Drain-Source Diode Forward Current -- -- 9.0 A S I Maximum Pulsed Drain-Source Diode Forward Current -- -- 36 A SM V V = 0 V, I = 9.0 A Drain-Source Diode Forward Voltage -- -- 1.5 V SD GS S t Reverse Recovery Time V = 0 V, I = 11.6 A, -- 128 -- ns rr GS S (Note 4) dI / dt = 100 A/s Q Reverse Recovery Charge -- 0.56 -- C rr F Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 3.9mH, I = 9.0A, V = 50V, R = 25 , Starting T = 25C AS DD G J 3. I 11.6A, di/dt 300A/ s, V BV Starting T = 25C SD DD DSS, J 4. Pulse Test : Pulse width 300 s, Duty cycle 2% 5. Essentially independent of operating temperature 2009 Fairchild Semiconductor Corporation Rev. A2, January 2009