FXLH1T45 Level Translator, 1-Bit Bidirectional Configurable Voltage Supplies and Bushold Data Inputs www.onsemi.com The FXLH1T45 is a single bit configurable dualvoltage supply translator designed for both unidirectional and bidirectional voltage translation between two logic levels. The device allows translation between voltages as high as 3.6 V to as low as 1.1 V. The A port tracks the V level, and the B port tracks the V level. This allows for CCA CCB bidirectional voltage translation over a variety of voltage levels: 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The device remains in 3STATE until both V s reach active levels CC SIP6 1.45x1.0 allowing either V to be poweredup first. Internal power down CC CASE 127EB control circuits place the device in 3STATE if either V is removed. CC The Transmit/Receive (T/R) input determines the direction of data flow through the device. The FXLH1T45 is designed so that the MARKING DIAGRAM control pin (T/R) is supplied by V . CCA Features XDKK Bidirectional Interface between any 2 Levels from 1.1 V to 3.6 V XYZ Fully Configurable: Inputs Track V level CC Nonpreferential Powerup Sequencing either V may be CC Poweredup First XD = Device Code Outputs Remain in 3STATE until Active V Level is Reached CC KK = Lot Code Outputs Switch to 3STATE if either VCC is at GND XY = Numeric Date Code Z = Assembly Plant Code Power Off Protection Bushold On Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors ORDERING INFORMATION Control Input (T/R) Levels are Referenced to V Voltage CCA See detailed ordering and shipping information on page 9 of Packaged in the MicroPak 6 SIP6 (1.0 mm x 1.45 mm) this data sheet. ESD Protections Exceeds: 4 kV HBM ESD (per JESD22A114 & Mil Std 883e 3015.7) 8 kV HBM I/O to GND ESD (per JESD22A114 & Mil Std 883e 3015.7) 1 kV CDM ESD (per ESD STM 5.3) 200 V MM ESD (per JESD22A115 & ESD STM5.2) Semiconductor Components Industries, LLC, 2006 1 Publication Order Number: March, 2019 Rev. 2 FXLH1T45/DFXLH1T45 FUNCTIONAL DIAGRAM POWERUP/POWERDOWN SEQUENCING FXL translators offer an advantage in that either V may CC be powered up first. This benefit derives from the chip V V CCA CCB design. When either V is at 0V, outputs are in a CC HIGHImpedance state. To ensure that bus contention, A excessive currents, or oscillations do not occur, a proper powerup sequence is recommended. B The recommended powerup sequence is the following: 1. Apply power to either V CC T/R 2. Apply power to the T/R input (Logic HIGH for AtoB operation Logic LOW for BtoA operation) and to the respective data inputs (A Port or B Port). This may occur at the same time as PINOUT Step 1 3. Apply power to other V CC 1 V 6 V CCA CCB The recommended powerdown sequence is the following: 2 GND 5 T/R 4. Remove power from either V CC 5. Remove power from other V CC 34 A B (Top Through View) PIN ASSIGNMENT Pin Number Terminal Name 1 V CCA 2 GND 3 A 4 B 5 T/R 6 V CCB PIN DESCRIPTIONS Pin Names Description T/R Transmit/Receive Input A Side A Input or Output B Side B Input or Output V Side A Power Supply CCA V Side B Power Supply CCB FUNCTION TABLE Inputs (T/R) Outputs L Bus B Data to Bus A H Bus A Data to Bus B H = HIGH Logic Level L = LOW Logic Level www.onsemi.com 2