LC75857E, LC75857W 1/3, 1/4-Duty LCD Driver with Key Input Function Overview The LC75857E and LC75857W are 1/3 duty and 1/4 duty LCD display www.onsemi.com drivers that can directly drive up to 164 segments and can control up to four general-purpose output ports. These products also incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. Features Key input function for up to 30 keys (A key scan is performed only when a key is pressed.) 1/3 duty and 1/4 duty drive schemes can be controlled from serial data. 1/2 bias and 1/3 bias drive schemes can be controlled from serial data. PQFP64 14x14 / QIP64E Capable of driving up to 126 segments using 1/3 duty and up to 164 LC75857E segments using 1/4 duty. Sleep mode and all segments off functions that are controlled from serial data. Switching between key scan output and segment output can be controlled from the serial data. The key scan operation enabled/disabled state can be controlled from the serial data. SPQFP64 10x10 / SQFP64 Switching between segment output port and general-purpose output port LC75857W can be controlled from serial data. The common and segment output waveform frame frequency can be controlled from the serial data. Switching between RC oscillator mode and external clock mode can be controlled from the serial data. Serial data I/O supports CCB* format communication with the system controller. Direct display of display data without the use of a decoder provides high generality. Independent VLCD for the LCD driver block. (When the logic block supply voltage VDD is in the range 3.6 to 6.0 V, VLCD can be set to a voltage in the range 0.75 VDD to 6.0 V, and when VDD is in the range 2.7 to 3.6 V, VLCD can be set to a voltage in the range 2.7 to 6.0 V.) Provision of an on-chip voltage-detection type reset circuit prevents incorrect displays. * Computer Control Bus (CCB) is an ON Semiconductors original bus format and the bus addresses are controlled by ON Semiconductor. ORDERING INFORMATION See detailed ordering and shipping information on page 42 of this data sheet. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number : July 2017 - Rev. 1 LC75857E W/D LC75857E, LC75857W Specifications Absolute Maximum Ratings at Ta=25C, V =0V SS Parameter Symbol Conditions Ratings Unit V max V 0.3 to +7.0 V DD DD Maximum supply voltage V max V 0.3 to +7.0 LCD LCD V 1 CE, CL, DI 0.3 to +7.0 IN Input voltage V 2 OSC,TEST 0.3 to V +0.3 V IN DD V3V 1, V 2, KI1 to KI5 0.3 to V +0.3 IN LCD LCD LCD V 1 DO 0.3 to +7.0 OUT Output voltage V 2 OSC 0.3 to V +0.3 V OUT DD V 3 S1 to S42, COM1 to COM4, KS1 to KS6, P1 to P4 0.3 to V +0.3 OUT LCD I 1 S1 to S42 300 A OUT I 2 COM1 to COM4 3 OUT Output current I 3 KS1 to KS6 1 mA OUT I 4 P1 to P4 5 OUT Allowable power dissipation Pd max Ta = 85C 200 mW Operating temperature Topr 40 to +85 C Storage temperature Tstg 55 to +125 C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. Allowable Operating Ranges at Ta = 40 to +85C, V =0V SS Ratings Parameter Symbol Conditions Unit min typ max V V 2.7 6.0 DD DD Supply voltage V : V = 3.6 V to 6.0 V 0.75 V 6.0 V LCD DD DD V LCD V : V = 2.7 V to 3.6 V 2.7 6.0 LCD DD V 1V 1 2/3 V V LCD LCD LCD LCD Input voltage V V 2V 2 1/3 V V LCD LCD LCD LCD V 1 CE, CL, DI 0.8 V 6.0 IH DD Input high level voltage V 2 KI1 to KI5 0.6 V V V IH LCD LCD V 3 OSC: External clock mode 0.7 V V IH DD DD V 1 CE, CL, DI 0 0.2 V IL DD Input low level voltage V 2 KI1 to KI5 0 0.2 V V IL LCD V 3 OSC: External clock mode 0 0.3 V IL DD Recommended RC oscillator external resistor R OSC: RC oscillator mode 39 k OSC Recommended RC oscillator external capacitor C OSC: RC oscillator mode 1000 pF OSC Guaranteed RC oscillator operating range f OSC: RC oscillator mode 19 38 76 kHz OSC External clock frequency f OSC: External clock mode :Figure 4 19 38 76 kHz CK External clock duty D OSC: External clock mode :Figure 4 30 50 70 % CK Data setup time t CL, DI :Figures 2,3 160 ns ds Data hold time t CL, DI :Figures 2,3 160 ns dh CE wait time t CE, CL :Figures 2,3 160 ns cp CE setup time t CE, CL :Figures 2,3 160 ns cs CE hold time t CE, CL :Figures 2,3 160 ns ch High level clock pulse width t CL :Figures 2,3 160 ns H Low level clock pulse width t CL :Figures 2,3 160 ns L Rise time t CE, CL, DI :Figures 2,3 160 ns r Fall time t CE, CL, DI :Figures 2,3 160 ns f 1 DO output delay time t DO R =4.7 k, C =10pF * :Figures 2,3 1.5 s dc PU L 1 DO rise time t DO R =4.7 k, C =10pF * :Figures 2,3 1.5 s dr PU L Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor R and the load capacitance C . PU L Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 2