LV8127T Bi-CMOS LSI 3-phase Bipolar PWM Drive Pre-Driver IC www.onsemi.com for Brushless Motor Drive Overview LV8127T is a three-phase bipolar PWM drive pre-driver IC for N-channel High-side and Low-side FETs. This IC is optimized for low cost, high-efficiency drive circuits in applications that use motors with high drive currents. It offers high supply voltage capability and a high degree of flexibility. Feature User programmable output current limit TSSOP36 (275mil) Built-in protection circuits for Over temperature (OTP), Under Voltage Lock Out (UVLO), Locked rotor (CSD) and Output Current limit. Built-in Forward/Reverse direction control Built-in 5V regulator output Built-in 15V reference zener diode Hall IC input E-Brake function Typical Applications Power Tool Specifications Absolute Maximum Ratings at Ta = 25C Parameter Symbol Conditions Ratings Unit Supply voltage 1 V max V terminal 23 V CC CC Supply voltage 2 VM max VM terminal 190 V Supply voltage 3 VG max UH, VH and WH 210 V DC Output current 1 I max1 UL, VL and WL 50 mA DC O DC Output current 2 I max2 UOUT, VOUT and WOUT, Source current 50 mA DC O DC Output current 3 I max3 UOUT, VOUT and WOUT, Sink current 50 mA DC O RF pin input voltage V max 1 V RF LVS pin input voltage V max The pins LVS1 and LVS2 V5+0.3 V LVS IN pin input voltage V max The pins IN1, IN2 and IN3 V5+0.3 V IN HSEL pin input voltage V max V5+0.3 V HSEL F/R pin input voltage V max V5+0.3 V FR + V + max V5+0.3 V EI pin input voltage EI Allowable power dissipation Pd max * 1.1 W Operation temperature Topr Ta 30 to +100 C Storage temperature Tstg 55 to +150 C *When mounted on the specified printed circuit board (114.3 76.1 1.6mm), Glass epoxy Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ORDERING INFORMATION See detailed ordering and shipping information on page 23 of this data sheet. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number : December 2014 - Rev. 2 LV8127T/D LV8127T Recommended Operating Conditions at Ta = 25C Parameter Symbol Conditions Ratings Unit Supply voltage 1 V V terminal 12 to 18 V CC CC Supply voltage 2 VM VM terminal 18 to 185 V Supply voltage 3 VG The pins UH, VH and WH V +VM V CC 5V constant output current I V5 V5 terminal 30 mA Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Electrical Characteristics at Ta = 25C, VM = 48V, V = 16V CC Ratings Parameter Symbol Conditions Unit min typ max Current drain I 4 5.5mA CC 5V Regulator (V5 terminal) Output voltage V5REG I = 5mA 4.7 5 5.3 V O Line regulation V5REG1 V = 12 to 20V 15 50 mV CC Load regulation V5REG2 I = 5 to 30mA 10 70 mV O Gate Drive Outputs (UFG = VFG = WFG = 0V, UH = VH = WH = 15V when V = 16V) *Note1 CC Low Side Driver High Side On LS UL, VL and, WL I = 10mA 25 35 RonH OH Resistance Low Side Driver Low Side On LS UL, VL and, WL I = 10mA 25 35 RonL OL Resistance High Side Driver High Side On HS UOUT, VOUT and, WOUT I = 10mA 25 35 RonH OH Resistance High Side Driver Low Side On HS UOUT, VOUT and, WOUT I = 10mA 10 15 RonL OH Resistance High Side dead time1 Tdelay1 UOUT, VOUT and WOUT (see figure X) 2.9 4 5.1 S Low Side dead time2 Tdelay2 UL, VL and WL (see figure X) 3.4 4.7 6.1 S PWM Oscillator (PWM terminal) High level output voltage V (PWM) 2.75 3.0 3.25 V OH Low level output voltage V (PWM) 1.0 1.1 1.2 V OL External capacitor charge current ICHG VPWM = 2.1V 55 43 30 A Oscillation frequency f(PWM) C = 1000pF 15.5 20 24.5 kHz Amplitude V(PWM) 1.65 1.9 2.15Vp-p Low Voltage Shutdown (LVSD) LVS1 threshold voltage VLVS1 1.8 2.0 2.2 V LVS2 Hysteresis driver On resistance VLVS2L ILVS2 = 5mA 15 30 Output leakage current ILVS2leak VLVS2 = 5V 10 A + Output Current Control Voltage Input (EI terminal) Gain (VEI+/VRF) GDFSL0 V + 1.27V(typ) 0 V/V EI Gain (VEI+/VRF) GDFSL1 1.27(typ) < V + 3V(typ) 0.025 0.03 0.035 Times EI Gain (VEI+/VRF) GDFSL2 3.51(typ) V + 3V(typ) 0.08 0.095 0.116Times EI Reference Voltage Clamp V V + 3.51V(typ) 90 105 120 mV RF EI max Control voltage input range VSLEI 0 V5 V Over Temperature Protection (OTP) OTP threshold TSD Design target value (junction temperature) 150 170 C Hysteresis TSD Design target value (junction temperature) 30 C *Note1:Gate driver output Iopeak=640mA (t<20 sec duty<7% VCC=16V) Continued on next page