MC10E104, MC100E104
5 V ECL Quint 2Input
AND/NAND Gate
Description
The MC10E/100E104 is a quint 2-input AND/NAND gate. The
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function output F is the OR of all five AND gate outputs, while F is the
NOR. The Q outputs need not be terminated if only the F outputs are to be
used.
The 100 Series contains temperature compensation.
Features
600 ps Max. Propagation Delay PLCC28
FN SUFFIX
OR/NOR Function Outputs
CASE 77602
PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
with V = 0 V
EE
NECL Mode Operating Range: V = 0 V
CC
MARKING DIAGRAM*
with V = 4.2 V to 5.7 V
EE
1
Internal Input 50 k Pulldown Resistors
ESD Protection:
MCxxxE104G
> 2 kV Human Body Model
AWLYYWW
> 200 V Machine Model
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity: Level 3 (Pb-Free)
xxx = 10 or 100
(For Additional Information, see Application Note AND8003/D)
A = Assembly Location
Flammability Rating: UL 94 V0 @ 0.125 in,
WL = Wafer Lot
Oxygen Index: 28 to 34
YY = Year
WW = Work Week
Transistor Count = 134 Devices
G = Pb-Free Package
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device Package Shipping
MC10E104FNG PLCC28 37 Units / Tube
(Pb-Free)
MC10E104FNR2G PLCC28 500 Tape & Reel
(Pb-Free)
MC100E104FNR2G PLCC28
500 Tape & Reel
(Pb-Free)
For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
July, 2016 Rev. 8 MC10E104/DMC10E104, MC100E104
D D D NC V F F
3a 4b 4a CCO
F
25 24 23 22 21 20 19
F
18
D 26 Q
3b 4
D
Q
D 17 Q 0a 0
27
2a 4
D Q
0b
0
D 28 16
2b V
CC
D Q
1a 1
1
V 15
Q
EE
3
D Q
1b
1
D
2 14
1a Q
3
D Q
2a 2
D 3 13
Q
1b
2
D Q
2b
2
D
4
0a 12 Q
2
D Q
3a 3
56 7 8 9 10 11
D Q
3b 3
D V Q Q Q Q V
0b CCO 0 0 1 1 CCO
D Q
4a 4
All V and V pins are tied together on the die.
CC CCO
D Q
4b
4
Warning: All V , V , and V pins must be externally
CC CCO EE
connected to Power Supply to guarantee proper operation.
Figure 2. Logic Diagram
Figure 1. 28-Lead Pinout (Top View)
Table 1. PIN DESCRIPTION
PIN FUNCTION
D D ECL Data Inputs
0a 4b
Q Q ECL AND Outputs
0 4
Q Q ECL NAND Outputs
0 4
F ECL OR Output
F ECL NOR Output
V , V Positive Supply
CC CCO
V Negative Supply
EE
NC No Connect
Table 2. FUNCTION OUTPUTS
F = (D D ) + (D D ) + (D D ) +
0a 0b 1a 1b 2a 2b
(D D ) + (D D )
3a 3b 4a 4b
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2