MC10E136, MC100E136 5 VECL 6Bit Universal Up/Down Counter Description The MC10E/100E136 is a 6-bit synchronous, presettable, cascadable universal counter. The device generates a look-ahead-carry www.onsemi.com output and accepts a look-ahead-carry input. These two features allow for the cascading of multiple E136s for wider bit width counters that operate at very nearly the same frequency as the stand alone counter. The CLOUT output will pulse LOW for one clock cycle one count before the E136 reaches terminal count. The COUT output will pulse LOW for one clock cycle when the counter reaches terminal count. PLCC28 For more information on utilizing the look-ahead-carry features of the FN SUFFIX device please refer to the applications section of this data sheet. The CASE 77602 differential COUT output facilitates the E136s use in programmable divider and self-stopping counter applications. Unlike the H136 and other similar universal counter designs, the E136 MARKING DIAGRAM* carry-out and look-ahead-carry-out signals are registered on chip. 1 This design alleviates the glitch problem seen on many counters where the carry out signals are merely gated. Because of this architecture there are some minor functional differences between the MCxxxE136G E136 and H136 counters. The user, regardless of familiarity with the AWLYYWW H136, should read this data sheet carefully. Note specifically (see logic diagram) the operation of the carry out outputs and the look-ahead-carry in input when utilizing the master reset. xxx = 10 or 100 When left open all of the input pins will be pulled LOW via an input A = Assembly Location pull-down resistor. The master reset is an asynchronous signal which WL = Wafer Lot when asserted will force the Q outputs LOW. YY = Year The Q outputs need not be terminated for the E136 to function WW = Work Week properly, in fact if these outputs will not be used in a system it is G = Pb-Free Package recommended to save power and minimize noise that they be left *For additional marking information, refer to open. This practice will minimize switching noise which can reduce Application Note AND8002/D. the maximum count frequency of the device or significantly reduce margins against other noise in the system. ORDERING INFORMATION See detailed ordering and shipping information on page 10 Features of this data sheet. 550 MHz Count Frequency Fully Synchronous Up and Down Counting Moisture Sensitivity: Level 3 (Pb-Free) Look-Ahead-Carry Input and Output (For Additional Information, see Application Asynchronous Master Reset Note AND8003/D) PECL Mode Operating Range: V = 4.2 V to 5.7 V CC Flammability Rating: UL 94 V0 with V = 0 V EE 0.125 in, Oxygen Index: 28 to 34 NECL Mode Operating Range: V = 0 V CC Transistor Count = 506 Devices with V = 4.2 V to 5.7 V EE These Devices are Pb-Free, Halogen Free Internal Input 50 k Pulldown Resistors and are RoHS Compliant ESD Protection: > 2 kV Human Body Model > 200 V Machine Model Meets or Exceeds JEDEC Standard EIA/JESD78, IC Latchup Test Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 10 MC10E136/DMC10E136, MC100E136 D3 D4 D5 V Q5 Q4 V CCO CCO 25 24 23 22 21 20 19 26 18 D2 Q3 17 S2 27 Q2 S1 28 16 V CC V 1 15 EE V CCO Pinout: 28-lead PLCC (Top View) CLK 14 2 COUT 13 CIN 3 COUT CLIN 12 4 CLOUT 5 6 7 8 9 10 11 D1 MR D0 V Q0 Q1 V CCO CCO * All V and V pins are tied together on the die. CC CCO Warning: All V , V , and V pins must be externally con- CC CCO EE nected to Power Supply to guarantee proper operation. Figure 1. 28-Lead Pinout Table 1. PIN DESCRIPTION PIN FUNCTION D D ECL Preset Data Inputs 0 5 Q Q ECL Data Outputs 0 5 S1, S2 Mode Control Pins MR Master Reset CLK ECL Clock Input COUT, ECL Differential Carry-Out Output (Active COUT LOW) CLOUT ECL Look-Ahead-Carry Out (Active LOW) CIN ECL Carry-In Input (Active LOW) CLIN ECL Look-Ahead-Carry In Input (Active LOW) V , V Positive Supply CC CCO V Negative Supply EE Table 2. FUNCTION TABLE (Expanded Truth Table on page 3) S1 S2 CIN MR CLK FUNCTION L L X L Z Preset Parallel Data L H L L Z Increment (Count Up) L H H L Z Hold Count H L L L Z Decrement (Count Down) H L H L Z Hold Count H H X L Z Hold Count X X X H X Reset (Qn = LOW) Figure 2. E136 Universal Up/Down Counter Logic Diagram www.onsemi.com 2 S1 S2 QM0 DQ COUT Q COUT S CIN DQ DQ DQ CLIN DQ Bits 2 - 4 Q Q Q R R R S CLOUT DQ S QM1 QM0 MR CLK D0 Q0 D1 Q1 D2 - D4 Q2 - Q4 D5 Q5 Note that this diagram is provided for understanding of logic operation only. It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.