MC100EL17 5 VECL Quad Differential Receiver Description The MC100EL17 is a low-voltage, quad differential receiver. The device is functionally equivalent to the E116 device www.onsemi.com Under open input conditions, the D input will be biased at V /2 and the CC D input will be pulled down to V . This operation will force the Q output EE LOW and ensure stability. The V pin, an internally generated voltage supply, is available to this BB device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. V may also BB BB rebias AC coupled inputs. When used, decouple V and V via a BB CC 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When SOIC20 WB not used, V should be left open. BB DW SUFFIX CASE 751D05 Features 325 ps Propagation Delay The 100 Series Contains Temperature Compensation MARKING* DIAGRAM PECL Mode Operating Range: V = 4.2 V to 5.7 V with V = 0 V CC EE NECL Mode Operating Range: V = 0 V with V = 4.2 V to 5.7 V CC EE 20 Internal Input Pulldown Resistors on D Inputs, Pullup and Pulldown Resistors on D Inputs 100EL17 Q Output will Default LOW with Inputs Open or at V EE AWLYYWWG These Devices are Pb-Free, Halogen Free and are RoHS Compliant 1 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100EL17DWG SOIC20 WB 38 Units/Tube (Pb-Free) Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 8 MC100EL17/DMC100EL17 V Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 V CC EE Table 1. PIN DESCRIPTION 20 19 18 17 16 15 14 13 12 11 PIN FUNCTION Dn, Dn ECL Differential Data Inputs Qn, Qn ECL Differential Data Outputs V Reference Voltage Output BB V Positive Supply CC V Negative Supply EE 1 2 3 4 5678 9 10 V D0 D0 D1 D1 D2 D2 D3 D3 V CC BB * All V pins are tied together on the die. CC Warning: All V and V pins must be externally connected to Power CC EE Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: (Top View) Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 K Internal Input Pullup Resistor 75 K ESD Protection Human Body Model > 2 KV Machine Model > 200 V Charged Device Model > 4 V Moisture Sensitivity (Note 1) Level 3 Pb-Free Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 141 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Units V PECL Mode Power Supply V = 0 V 8 V CC EE V NECL Mode Power Supply V = 0 V 8 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 CC I EE I Output Current Continuous 50 mA out Surge 100 I V Sink/Source 0.5 mA BB BB T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC-20 WB 90 C/W JA 500 lfpm 60 Thermal Resistance (Junction-to-Case) Standard Board SOIC-20 WB 30 to 35 C/W JC T Wave Solder (Pb-Free) <2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2