MC10EP05, MC100EP05
3.3V / 5VECL 2Input
Differential AND/NAND
Description
The MC10/100EP05 is a 2-input differential AND/NAND gate. The
device is functionally equivalent to the EL05 and LVEL05 devices.
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With AC performance much faster than the LVEL05 device, the EP05
is ideal for applications requiring the fastest AC performance
8 8
available.
1
The 100 Series contains temperature compensation. 1
SOIC8NB TSSOP8
Features
DFN8
D SUFFIX DT SUFFIX
MN SUFFIX
220 ps Typical Propagation Delay
CASE CASE
CASE 506AA
75107 948R02
Maximum Frequency > 3 GHz Typical
PECL Mode Operating Range:
V = 3.0 V to 5.5 V with V = 0 V
CC EE
NECL Mode Operating Range:
MARKING DIAGRAMS*
V = 0 V with V = 3.0 V to 5.5 V
CC EE
8
8
Open Input Default State
HEP05
HP05
Safety Clamp on Inputs
ALYW
ALYW
Q Output Will Default LOW with Inputs Open or at V
EE 14
1
1
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
8
8
KEP05
KP05
ALYW
ALYW
14
1
1
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5I = MC10 Y = Year
2X = MC100 W = Work Week
D = Date Code = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information on page 8 of
this data sheet.
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
July, 2016 Rev. 10 MC10EP05/D
2X D 5I D
MC10EP05, MC100EP05
Table 1. PIN DESCRIPTION
1 8 Pin Function
D V
0 CC
D0*, D1*, D0**, D1** ECL Data Inputs
Q, Q ECL Data Outputs
V Positive Supply
D 2 7 Q CC
0
V Negative Supply
EE
EP (DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
6
D 3 Q
1
to the most negative supply (GND) or
leave unconnected, floating open.
* Pins will default LOW when left open.
** Pins will default to V /2when left open.
CC
D45 V
1 EE
Table 2. TRUTH TABLE
D0 D1 D0 D1 Q Q
Figure 1. 8-Lead Pinout (Top View) and Logic
L L H H L H
Diagram
L H H L L H
H L L H L H
H H L L H L
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor 37.5 k
ESD Protection
Human Body Model > 4 kV
Machine Model > 200 V
Charged Device Model > 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC8NB Level 1
TSSOP8 Level 3
DFN8 Level 1
Flammability Rating UL 94 V0 @ 0.125 in
Oxygen Index: 28 to 34
Transistor Count 137 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2