MC100EP101FAG ON Semiconductor

MC10EP101, MC100EP101 3.3V / 5VECL Quad 4Input OR/NOR Description The MC10/100EP101 is a Quad 4input OR/NOR gate. The device is functionally equivalent to the E101. With AC performance faster MC10EP101, MC100EP101 D0d D1a D1b D1c D1d D2a D2b D2c V V Q0 Q0 V D0a D0b D0c CC CC EE 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 25 16 D0c D2d 1 V 24 D0d CC 26 15 D0b D3a Q1 2 23 D1a 27 14 22 D1b D0a D3b Q1 3 28 13 Q2 4 21 D1c V V EE CC MC10EP101 MC10EP101 MC100EP101 29 12 5 20 Q0 D3c Q2 D1d MC100EP101 30 11 6 Q0 D3d Q3 19 D2a Q3 7 31 10 18 D2b V V CC EE V 8 17 D2c 32 9 CC V NC CC 12345678 9 10 11 12 13 14 15 16 NC V D3d D3c V D3b D3a D2d EE CC V Q1 Q1 Q2 Q2 Q3 Q3 V CC CC Figure 2. 32Lead QFN Pinout (Top View) Warning: All V and V pins must be externally connected to CC EE Power Supply to guarantee proper operation. Figure 1. 32Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION D 0a PIN FUNCTION D Q 0b 0 D D0a* D3d* ECL Data Inputs 0c Q 0 D 0d Q0Q3, Q0Q3 ECL Data Outputs V Positive Supply D CC 1a D Q 1b V Negative Supply 1 EE D 1c Q 1 NC No Connect D 1d EP for QFN32, The Exposed Pad (EP) on the only QFN32 package bottom is thermally connected to the die D 2a for improved heat transfer out Q D 2 2b of package. The exposed pad must be attached to a heat D Q 2c 2 sinking conduit. The pad is D 2d electrically connected to V . EE * Pins will default LOW when left open. D 3a Q D 3 3b D Table 2. TRUTH TABLE Q 3c 3 D 3d Dna Dnb Dnc Dnd Qn Qn V EE LL L L L H H XXX H L XH X X H L X X HX HL Figure 3. Logic Diagram X XXH H L H HHH HL