3.3 V/5 VECL Differential Receiver/Driver with High Gain and Enable Output MC100EP16VC Description www.onsemi.com The EP16VC is a differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high 8 gain and enable output. 1 The EP16VC provides an EN input which is synchronized with the TSSOP8 data input (D) signal in a way that provides glitchless gating of the DT SUFFIX QHG and QHG outputs. CASE 948R02 When the EN signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and MARKING DIAGRAM* EN goes HIGH, it will force the Q LOW and the Q HIGH on the HG HG next negative transition of the data input. If the data input is LOW 8 when the EN goes HIGH, the next data transition to a HIGH is ignored and Q remains LOW and Q remains HIGH. The next positive HG HG KP66 transition of the data input is not passed on to the data outputs under ALYW these conditions. The Q and Q outputs remain in their disabled HG HG 1 state as long as the EN input is held HIGH. The EN input has no influence on the Q output and the data input is passed on (inverted) to this output whether EN is HIGH or LOW. This configuration is ideal A = Assembly Location L = Wafer Lot for crystal oscillator applications where the oscillator can be free Y = Year running and gated on and off synchronously without adding extra W = Work Week counts to the output. = Pb-Free Package The V /D pin is internally dedicated and available for differential BB (Note: Microdot may be in either location) interconnect. V /D may rebias AC coupled inputs. When used, BB decouple V /D and V via a 0.01 F capacitor and limit current *For additional marking information, refer to BB CC Application Note AND8002/D. sourcing or sinking to 1.5 mA. When not used, V /D should be left BB open. The 100 Series contains temperature compensation. ORDERING INFORMATION Features Device Package Shipping 310 ps Typical Prop Delay Q, MC100EP16VCDTR2G TSSOP8 2500 / 380 ps Typical Prop Delay QHG, QHG (PbFree) Tape & Reel Gain > 200 For information on tape and reel specifications, Maximum Frequency > 3 GHz Typical including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications PECL Mode Operating Range: Brochure, BRD8011/D. V = 3.0 V to 5.5 V with V = 0 V CC EE NECL Mode Operating Range: V = 0 V with V = 3.0 V to 5.5 V CC EE Open Input Default State Q Output Will Default LOW with D Inputs Open or at V HG EE V Output BB These Devices are PbFree, Halogen Free and are RoHS Compliant Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2021 Rev. 9 MC100EP16VC/DMC100EP16VC Table 1. PIN DESCRIPTION Q 1 8 V CC Pin Function D* ECL Data Input Q ECL Data Output D 2 7 Q HG Q , Q ECL High Gain Data Outputs HG HG EN* ECL Enable Input V /D Reference Voltage Output / ECL Data Input BB 3 6 Q V Positive Supply HG CC V /D BB V Negative Supply EE OE Q LEN *Pins will default LOW when left open. V BB LATCH 45 V EN EE D Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg TSSOP8 Level 3 Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 167 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2