3.3 V ECL Programmable Delay Chip MC100EP195B Descriptions The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. www.onsemi.com The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay MARKING increment of the EP195B has a digitally selectable resolution of about DIAGRAMS* 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D 9:0 values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of MC100 real time delay values by D 9:0 . A LOW to HIGH transition on LEN EP195B will LOCK and HOLD current values present against any subsequent AWLYYWWG LQFP32 changes in D 10:0 . The approximate delay values for varying tap FA SUFFIX 32 numbers correlating to D0 (LSB) through D9 (MSB) are shown in CASE 561AB 1 Table 6 and Figure 3. The IN/IN inputs can accept LVPECL (SE of Diff), or LVDS level signals. Because the EP195B is designed using a chain of multiplexers 1 it has a fixed minimum delay of 2.2 ns. An additional pin D10 is MC100 provided for controlling Pins 14 and 15, CASCADE and CASCADE, 32 1 EP195B also latched by LEN, in cascading multiple PDCs for increased ALYW QFN32 programmable range. The cascade logic allows full control of multiple MN SUFFIX PDCs. Switching devices from all 1 states on D 0:9 with SETMAX CASE 488AM LOW to all 0 states on D 0:9 with SETMAX HIGH will increase A = Assembly Location the delay equivalent to D0, the minimum increment. WL, L = Wafer Lot Select input pins D 10:0 may be threshold controlled by Y, YY = Year combinations of interconnects between V (pin 7) and V (pin 8) EF CF W, WW = Work Week for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input G or = PbFree Package levels, leave V and V open. For ECL operation, short V and CF EF CF (Note: Microdot may be in either location) V (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V EF *For additional marking information, refer to supply reference to V and leave open V pin. The 1.5 V reference CF EF Application Note AND8002/D. voltage to V pin can be accomplished by placing a 2.2 k resistor CF between V and V for a 3.3 V power supply. CF EE ORDERING INFORMATION The V pin, an internally generated voltage supply, is available to BB this device only. For singleended input conditions, the unused Device Package Shipping differential input is connected to V as a switching reference voltage. BB MC100EP195BFAG LQFP32 250 Units / V may also rebias AC coupled inputs. When used, decouple V BB BB (PbFree) Tray and V via a 0.01 F capacitor and limit current sourcing or sinking CC to 0.5 mA. When not used, V should be left open. MC100EP195BMNG QFN32 74 Units / BB (PbFree) Rail The 100 Series contains temperature compensation. Features Maximum Input Clock Frequency >1.2 GHz Typical IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels Programmable Range: 0 ns to 10 ns A Logic High on the EN Pin Will Force Q to Logic Low Delay Range: 2.2 ns to 12.2 ns D 10:0 Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels 10 ps Increments V Output Reference Voltage PECL Mode Operating Range: BB These are PbFree Devices V = 3.0 V to 3.6 V with V = 0 V CC EE NECL Mode Operating Range: V = 0 V with V = 3.0 V to 3.6 V CC EE Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: March, 2021 Rev. 3 MC100EP195B/DEN D1 EN D1 CASCADE D2 D2 CASCADE CASCADE D3 D3 CASCADE V V CC V V EE CC EE SETMAX D4 SETMAX D4 SETMIN D5 SETMIN D5 LEN D6 LEN D6 V D7 EE V D7 EE MC100EP195B 32 31 30 29 28 27 26 25 24 D8 V 1 EE 23 D9 2 D0 22 D10 3 V CC 21 4 Q IN MC100EP195B 20 IN Q 5 19 V V 6 CC BB 18 V V CC EF 7 17 V 8 NC CF 9 10 11 12 13 14 15 16 Figure 1. 32Lead LQFP Pinout (Top View) 32 31 30 29 28 27 26 25 1 24 V D8 EE 2 23 D0 D9 3 22 V D10 CC 4 21 Q IN MC100EP195B 5 20 Q IN V 6 19 CC V BB V 7 18 V CC EF 8 17 NC V CF 9 10 11 12 1314 1516 Exposed Pad (EP) Figure 1. 32 Lead QFN (Top View) www.onsemi.com 2