MC100EP210SFAG ON Semiconductor

MC100EP210S 2.5V1:5 Dual Differential LVDS Compatible Clock Driver Description MC100EP210S Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1 V Qa0 Qa0 Qa1 Qa1 Qa2 Qa2 V CC CC 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 V 24 Qa3 EE 25 16 V V CC CC VTA 2 23 Qa3 26 15 Qa2 Qb2 22 Qa4 27 14 CLKa 3 Qa2 Qb2 28 13 CLKa 4 21 Qa4 Qa1 Qb3 MC100EP210S MC100EP210S 29 12 Qa1 Qb3 5 20 VTB Qb0 30 11 Qa0 Qb4 6 CLKb 19 Qb0 31 10 Qa0 Qb4 CLKb 7 18 Qb1 32 9 V V CC CC V 8 17 Qb1 EE 1 2345678 9 10 11 12 13 14 15 16 V Qb4 Qb4 Qb3 Qb3 Qb2 Qb2 V CC CC V VTA VTB V EE EE Figure 1. 32Lead QFN Pinout (Top View) Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. 32 Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION PIN FUNCTION CLKn, CLKn LVDS, LVPECL CLK Inputs* Qn0:4, Qn0:4 LVDS Outputs VTA 50 Termination Resistors VTB 50 Termination Resistors V Positive Supply CC V Ground EE EP for QFN32, The Exposed Pad (EP) on the QFN32 package bottom is only thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat sinking conduit. The pad is electrically connected to V . EE *Under open or floating conditions with input pins converging to a common termination bias voltage the device is susceptible to auto oscillation. VTA VTB Qa0 Qb0 Qa0 Qb0 50 50 50 50 Qa1 Qb1 CLKa CLKb Qa1 Qb1 CLKa CLKb Qa2 Qb2 Qa2 Qb2 Qa3 Qb3 Qa3 Qb3 Qa4 Qb4 Qa4 Qb4 Figure 2. Logic Diagram