MC100EPT21DR2 ON Semiconductor

MC100EPT21 3.3VDifferential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator The MC100EPT21 is a Differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), MC100EPT21 Table 1. PIN DESCRIPTION NC 1 8 V CC PIN FUNCTION Q LVTTL/LVCMOS Output LVTTL D*, D* Differential LVPECL/LVDS/CML Input D 2 7 Q V Positive Supply CC V Output Reference Voltage BB GND Ground D 3 6 NC NC No Connect LVPECL (DFN8 only) Thermal exposed pad must be EP connected to a sufficient thermal conduit. Elec- V45 GND BB trically connect to the most negative supply (GND) or leave unconnected, floating open. * Pin will default to 1/2 of V when left open. CC Figure 1. Logic Diagram and 8Lead Pinout (Top View) Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor D 50 k Internal Input Pulldown Resistor D 50 k Internal Input Pullup Resistor D, D 50 k ESD Protection Human Body Model > 1.5 kV Machine Model > 100 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC8 Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 81 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D.