MC100EPT22 3.3 VDual LVTTL/LVCMOS to Differential LVPECL Translator Description www.onsemi.com The MC100EPT22 is a dual LVTTL/LVCMOS to differential LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8lead 8 8 package and the single gate of the EPT22 makes it ideal for those 1 1 applications where space, performance, and low power are at a premium. Because the mature MOSAIC 5 process is used, low cost SOIC8 NB TSSOP8 DFN8 D SUFFIX DT SUFFIX MN SUFFIX and high speed can be added to the list of features. CASE 75107 CASE 948R02 CASE 506AA Features 420 ps Typical Propagation Delay MARKING DIAGRAMS* Maximum Frequency = > 1.1 GHz Typical 8 8 Operating Range: V = 3.0 V to 3.6 V with GND = 0 V CC KPT22 KA22 PNP LVTTL Inputs for Minimal Loading ALYW ALYW Q Output Will Default HIGH with Inputs Open 14 1 1 The 100 Series Contains Temperature Compensation. These Devices are Pb-Free, Halogen Free and are RoHS Compliant SOIC8 NB TSSOP8 DFN8 A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100EPT22DG SOIC8 NB 98 Units/Tube (Pb-Free) MC100EPT22DR2G SOIC8 NB 2500 Tape & Reel (Pb-Free) MC100EPT22DTG TSSOP8 100 Tape & Reel (Pb-Free) MC100EPT22DTR2G 2500 Tape & Reel TSSOP8 (Pb-Free) MC100EPT22MNR4G DFN8 1000 Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 Rev. 14 MC100EPT22/D 3S M MC100EPT22 Table 1. PIN DESCRIPTION Q0 1 8 V CC PIN FUNCTION Q0, Q1, Q0, Q1 LVPECL Differential Outputs Q0 2 7 D0 D0, D1 LVTTL Inputs LVPECL LVTTL V Positive Supply CC Q1 3 6 D1 GND Ground EP (DFN8 only) Thermal exposed pad must be connected to a sufficient ther- Q145 GND mal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Figure 1. 8Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8 NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 164 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2