MC100EPT24DTG ON Semiconductor

MC100EPT24 3.3 VLVTTL/LVCMOS to Differential LVECL Translator Description The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL www.onsemi.com translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a 3.3 V, +3.3 V and ground are required. The small outline 8-lead package and the single gate of the EPT24 makes it ideal for those applications where space, performance, and low power are at a 8 8 premium. 1 1 SOIC8 NB TSSOP8 DFN8 Features D SUFFIX DT SUFFIX MN SUFFIX 350 ps Typical Propagation Delay CASE 75107 CASE 948R02 CASE 506AA Maximum Input Clock Frequency = > 1.0 GHz Typical The 100 Series Contains Temperature Compensation MARKING DIAGRAMS* Operating Range: V = 3.0 V to 3.6 V V = 3.6 V to 3.0 V GND = 0 V CC EE 8 8 PNP LVTTL Input for Minimal Loading KPT24 Q Output will Default HIGH with Input Open KA24 ALYW ALYW These Devices are Pb-Free, Halogen Free and are RoHS Compliant 14 1 1 SOIC8 NB TSSOP8 DFN8 A = Assembly Location L = Wafer Lot Y = Year W = Work Week M = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100EPT24DG SOIC8 NB 98 Units / Tube (Pb-Free) MC100EPT24DR2G SOIC8 NB 2500 Tape & Reel (Pb-Free) TSSOP8 MC100EPT24DTG 100 Units / Tube (Pb-Free) MC100EPT24MNR4G DFN8 1000 Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 Rev. 10 MC100EPT24/D 3U M MC100EPT24 Table 1. PIN DESCRIPTION V 1 8 V EE CC PIN FUNCTION Q, Q Differential LVECL Outputs LVTTL D LVTTL Input D 2 7 Q V Positive Supply CC GND Ground LVECL V Negative Supply EE NC 3 6 Q NC No Connect EP (DFN8 only) Thermal exposed pad must be connected to a sufficient ther- NC45 GND mal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Figure 1. 8-Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor N/A Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8 NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 181 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2