MC100EPT23 3.3 VDual Differential LVPECL/LVDS/CML to LVTTL/LVCMOS Translator Description www.onsemi.com The MC100EPT23 is a dual differential LVPECL/LVDS/CML to LVTTL/LVCMOS translator. Because LVPECL (Positive ECL), LVDS, and positive CML input levels and LVTTL/LVCMOS output levels are used, only + 3.3 V and ground are required. The small 8 8 outline 8-lead SOIC package and the dual gate design of the EPT23 1 1 makes it ideal for applications which require the translation of a clock SOIC8NB TSSOP8 or data signal. DFN8 D SUFFIX DT SUFFIX MN SUFFIX The EPT23 is available in only the ECL 100K standard. Since there CASE CASE CASE 506AA are no LVPECL outputs or an external V reference, the EPT23 does BB 75107 948R02 not require both ECL standard versions. The LVPECL/LVDS inputs are differential. Therefore, the MC100EPT23 can accept any standard differential LVPECL/LVDS input referenced from a V of + 3.3 V. CC MARKING DIAGRAMS* Features 8 8 1.5 ns Typical Propagation Delay KPT23 KA23 ALYW Maximum Operating Frequency > 275 MHz ALYW 14 LVPECL/LVDS/CML Inputs, LVTTL/LVCMOS Outputs 1 1 24 mA LVTTL Outputs Operating Range: A = Assembly Location L = Wafer Lot V = 3.0 V to 3.6 V with GND = 0 V CC Y = Year These Devices are Pb-Free, Halogen Free and are RoHS Compliant W = Work Week M = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100EPT23DG SOIC8NB 98 Units/Tube (Pb-Free) MC100EPT23DR2G SOIC8NB 2500/Tape & Reel (Pb-Free) MC100EPT23DTG TSSOP8 100 Units/Tube (Pb-Free) MC100EPT23DTR2G TSSOP8 2500/Tape & Reel (Pb-Free) MC100EPT23MNR4G DFN8 1000/Tape & Reel (Pb-Free) For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: August, 2016 Rev. 19 MC100EPT23/D 3T M MC100EPT23 Table 1. PIN DESCRIPTION D0 1 8 V CC Pin Function Q0, Q1 LVTTL/LVCMOS Outputs D0**, D1** Differential LVPECL/LVDS/CML Inputs D0 2 7 Q0 D0**, D1** LVPECL LVTTL V Positive Supply CC GND Ground D1 3 6 Q1 EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating D145 GND open. ** Pins will default to V /2 when left open. CC (Top View) Figure 1. Logic Diagram and 8-Lead Pinout Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 50 k Internal Input Pullup Resistor 50 k ESD Protection Human Body Model > 1500 V Machine Model > 100 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 91 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V Power Supply GND = 0 V 3.8 V CC V Input Voltage GND = 0 V V V 3.8 V I I CC I Output Current Continuous 50 mA out Surge 100 T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8NB 190 C/W JA 500 lfpm 130 Thermal Resistance (Junction-to-Case) Standard Board SOIC8NB 41 to 44 C/W JC Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP8 185 C/W JA 500 lfpm 140 Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 C/W JC Thermal Resistance (Junction-to-Ambient) 0 lfpm DFN8 129 C/W JA 500 lfpm 84 www.onsemi.com 2