MC100LVE210FNG ON Semiconductor

MC100LVE210 3.3VECL Dual 1:4, 1:5 Differential Fanout Buffer Description The MC100LVE210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features MC100LVE210 Qa0 Qa0 Qa1 V Qa1 Qa2 Qa2 CCO Qa0 Qa0 25 24 23 22 21 20 19 CLKa Qa1 V 26 18 Qa3 EE CLKa Qa1 27 17 Qa3 V BB Qa2 Qb0 Qa2 CLKa 28 16 Qa3 Pinout: 28Lead PLCC V 15 V CC 1 CCO Qa3 (Top View) CLKa 2 14 Qb0 Qb0 3 13 Qb1 CLKb Qb0 CLKb 4 12 Qb1 CLKb Qb1 56 78 9 10 11 CLKb Qb1 Qb2 Qb4 Qb4 Qb3 V Qb3 Qb2 Qb2 CCO Qb2 Warning: All V , V , and V pins must be externally CC CCO EE Qb3 connected to Power Supply to guarantee proper operation. Qb3 Figure 1. Pinout Assignment Qb4 Qb4 Table 1. PIN DESCRIPTION V BB Pin Function CLKa, CLKa ECL Differential Input Pairs Figure 2. Logic Diagram CLKb, CLKb ECL Differential Input Pairs Qa0:3, Qa0:3 ECL Differential Outputs Qb0:3, Qb0:3 ECL Differential Outputs V Reference Voltage Output BB V , V Positive Supply CC CCO V Negative Supply EE Table 2. ATTRIBUTES Characteristic Value Internal Input Pulldown Resistor 50 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 2 kV Machine Model > 200 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) PbFree Pkg PLCC 28 Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 179 Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.