MC100LVEL13 3.3 VECL Dual 1:3 Fanout Buffer Description The MC100LVEL13 is a dual, fully differential 1:3 fanout buffer. The Low Output-Output Skew of the device makes it ideal for www.onsemi.com distributing two different frequency synchronous signals. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to V , The D input will bias EE around V /2 and the Q output will go LOW. CC Features SOIC20 WB 500 ps Typical Propagation Delays DW SUFFIX CASE 751D 50 ps Output-Output Skews ESD Protection: > 2 kV Human Body Model The 100 Series Contains Temperature Compensation MARKING DIAGRAM* PECL Mode Operating Range: V = 3.0 V to 3.8 V CC with V = 0 V EE 20 NECL Mode Operating Range: V = 0 V CC with V = 3.0 V to 3.8 V EE 100LVEL13 Internal Input Pulldown Resistors AWLYYWWG Q Output will Default LOW with Inputs Open or at V EE Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1 Moisture Sensitivity: Level 3 (Pb-Free) Flammability Rating: UL 94 V0 0.125 in, A = Assembly Location Oxygen Index: 28 to 34 WL = Wafer Lot YY = Year Transistor Count = 143 Devices WW = Work Week These Devices are Pb-Free, Halogen Free and are RoHS Compliant G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100LVEL13DWG SOIC20 WB 38 Units / Tube (Pb-Free) SOIC20 WB MC100LVEL13DWR2G 1000 (Pb-Free) Tape & Reel For information on tape and reel specifications, in- cluding part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 7 MC100LVEL13/DMC100LVEL13 Q1a Q1a Q2a Q2a V Q2b Q2b Q1b Q1b V CC EE Table 1. PIN DESCRIPTION 20 19 18 17 16 15 14 13 12 11 PIN FUNCTION Qna, Qna ECL Differential Clock Outputs Qnb, Qnb ECL Differential Clock Outputs CLKn, CLKn ECL Differential Clock Inputs V Positive Supply CC V Negative Supply EE 1 2 3 4 5 678 9 10 Q0a Q0a V CLKa CLKa CLKb CLKb V Q0b Q0b CC CC Warning: All V and V pins must be externally connected to CC EE Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View) Table 2. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 to 0 V CC EE V NECL Mode Power Supply V = 0 V 8 to 0 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 to 0 V I EE I CC V = 0 V V V 6 to 0 NECL Mode Input Voltage CC I EE V I Output Current Continuous 50 mA out Surge 100 T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC20 WB 90 C/W JA 500 lfpm SOIC20 WB 60 Thermal Resistance (Junction-to-Case) Standard Board SOIC20 WB 30 to 35 C/W JC T Wave Solder (Pb-Free) < 2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. www.onsemi.com 2