MC100LVEL16 3.3VECL Differential Receiver Description The MC100LVEL16 is a differential receiver. The device is functionally equivalent to the EL16 device, operating from a 3.3 V www.onsemi.com supply. The LVEL16 exhibits a wider V range than its EL16 IHCMR counterpart. With output transition times and propagation delays MARKING comparable to the EL16 the LVEL16 is ideally suited for interfacing DIAGRAMS* with high frequency sources at 3.3 V supplies. Under open input conditions, the Q input will be pulled down to V 8 EE 8 and the Q input will be biased to V /2. This condition will force the KVL16 CC 1 ALYW Q output low. SOIC8 D SUFFIX The V pin, an internally generated voltage supply, is available to BB 1 CASE 751 this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB 8 8 and V via a 0.01 F capacitor and limit current sourcing or sinking CC 1 KV16 to 0.5 mA. When not used, V should be left open. BB ALYW TSSOP8 DT SUFFIX Features 1 CASE 948R 300 ps Propagation Delay High Bandwidth Output Transitions The 100 Series Contains Temperature Compensation 1 4BM PECL Mode Operating Range: V = 3.0 V to 3.8 V CC DFN8 with V = 0 V EE MN SUFFIX NECL Mode Operating Range: V = 0 V CC CASE 506AA with V = 3.0 V to 3.8 V EE A = Assembly Location Internal Input Pulldown Resistors on D, Pullup and Pulldown L = Wafer Lot Resistors on D Y = Year Q Output will Default LOW with Inputs Open or at V W = Work Week EE M = Date Code These Devices are PbFree, Halogen Free/BFR Free and are RoHS = PbFree Package Compliant (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: July, 2015 Rev. 7 MC100LVEL16/DMC100LVEL16 Table 1. PIN DESCRIPTION NC 1 8 V CC PIN FUNCTION D, D ECL Data Inputs Q, Q ECL Data Outputs V Reference Voltage Output BB D 2 7 Q V Positive Supply CC V Negative Supply EE NC No Connect EP D 3 6 Q (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. V45 V BB EE Figure 1. Logic Diagram and Pinout Assignment Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 75 k ESD Protection Human Body Model > 4 KV Machine Model > 400 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time out of Drypack, PbFree Packages (Note 1) SOIC8 Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 79 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. Refer to Application Note AND8003/D for additional information. www.onsemi.com 2