3.3 VECL Quad Differential Receiver MC100LVEL17 Description The MC100LVEL17 is a 3.3 V ECL, quad differential receiver. The device is functionally equivalent to the E116 device with the capability www.onsemi.com of operation from either a 3.3 V or +3.3 V supply voltage. Under open input conditions, the D input will be biased at V /2 CC and the D input will be pulled down to V . This operation will force EE the Q output LOW and ensure stability. The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused SOIC20 WB differential input is connected to V as a switching reference voltage. BB DW SUFFIX V may also rebias AC coupled inputs. When used, decouple V BB BB CASE 751D05 and V via a 0.01 F capacitor and limit current sourcing or sinking CC to 0.5 mA. When not used, V should be left open. BB MARKING DIAGRAM* Features 325 ps Propagation Delay 20 High Bandwidth Output Transitions The 100 Series Contains Temperature Compensation 100LVEL17 AWLYYWWG PECL Mode Operating Range: V = 3.0 V to 3.8 V CC with V = 0 V EE NECL Mode Operating Range: V = 0 V CC 1 with V = 3.0 V to 3.8 V EE Internal Input Pulldown Resistors D Inputs A = Assembly Location Pullup and Pulldown on D Inputs WL = Wafer Lot YY = Year Q Output will Default LOW with Inputs Open or at V EE WW = Work Week These Devices are Pb-Free, Halogen Free and are RoHS Compliant G = Pb-Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION Device Package Shipping MC100LVEL17DWR2G SOIC20 WB 1000 / (Pb-Free) Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: March, 2016 Rev. 10 MC100LVEL17/DMC100LVEL17 V Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 V CC EE 20 19 18 17 16 15 14 13 12 11 Table 1. PIN DESCRIPTION PIN FUNCTION Dn, Dn ECL Differential Data Inputs Qn, Qn ECL Differential Data Outputs V Reference Voltage Output BB V Positive Supply CC V Negative Supply EE 1 2 3 4 5678 9 10 V D0 D0 D1 D1 D2 D2 D3 D3 V CC BB * All V pins are tied together on the die. CC Warning: All V and V pins must be externally connected to Power CC EE Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout: (Top View) Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 75 k ESD Protection Human Body Model > 2 kV Machine Model > 200 V Charged Device Model > 4 kV Moisture Sensitivity (Note 1) Level 3 Flammability Rating Oxygen Index: 28 to 34 UL 94 V0 0.125 in Transistor Count 141 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2