MC10E112
5VECL Quad Driver
Description
The MC10E112 is a quad driver with two pairs of OR/NOR outputs
from each gate, and a common, buffered enable input. Using the data
inputs the device can serve as an ECL memory address fan-out driver.
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Using just the enable input, the device serves as a clock driver,
although the MC10E/100E111 is designed specifically for this
purpose, and offers lower skew than the E112. For memory address
driver applications where scan capabilities are required, please refer to
the E212 device.
The 100 Series contains temperature compensation.
PLCC28
Features
FN SUFFIX
600 ps Max. Propagation Delay
CASE 77602
Common Enable Input
PECL Mode Operating Range:
V = 4.2 V to 5.7 V with V = 0 V
CC EE
MARKING DIAGRAM*
NECL Mode Operating Range:
1
V = 0 V with V = 4.2 V to 5.7 V
CC EE
Internal Input 50 k Pulldown Resistors
ESD Protection: MC10E112G
Human Body Model; > 2 kV AWLYYWW
Machine Model; > 200 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level: 3 (Pb-Free)
For Additional Information, see Application Note AND8003/D
A = Assembly Location
WL = Wafer Lot
Flammability Rating:
YY = Year
UL 94 V0 @ 0.125 in, Oxygen Index: 28 to 34
WW = Work Week
Transistor Count = 125 devices
G = Pb-Free Package
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
Device Package Shipping
MC10E112FNR2G PLCC28 500/Tape & Reel
(Pb-Free)
For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
July, 2016 Rev. 9 MC10E112/DMC10E112
Q Q Q Q V Q Q
3b 3a 3b 3a CCO 2b 2a
Q
0a
D
0
Q
25 24 23 22 21 20 19 0b
V 18 Q
Q
CCO 26 2b
0a
Q
0b
D 17 Q
3 27 2a
Q
1a
D
1 Q
D 16 1b
28 V
2
CC
Q
1a
1
V 15
Q
EE
Pinout: 28-Lead PLCC 1b
Q
1b
(Top View)
Q
2a
D 14
2 Q
1
1a
D
2
Q
2b
D 13
3 Q
0
1b
Q
2a
Q
2b
EN
4 Q
12
1a
Q
3a
D
567 89 10 11 3
Q
3b
Q
3a
NC V Q Q Q Q V
CCO 0a 0b 0a 0b CCO
Q
3b
*All V and V pins are tied together on the die.
CC CCO
EN
Warning: All V , V , and V pins must be externally
CC CCO EE
connected to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram
Figure 2. 28-Lead PLCC Pinout
Table 1. PIN DESCRIPTION
PIN FUNCTION
D D ECL Data Inputs
0 3
EN ECL Enable Input
Q , Q ECL True Outputs
na nb
Q , Q ECL Inverting Outputs
na nb
V , V Positive Supply
CC CCO
V Negative Supply
EE
NC No Connect
Table 2. Truth Table
EN D Q Q
L H H L
H H H L
L L L H
H L H L
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