MC10EL11, MC100EL11 5.0 VECL 1:2 Differential Fanout Buffer The MC10EL/100EL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. The within-device skew and propagation delay is www.onsemi.com significantly improved over the E111. The differential inputs of the EL11 employ clamping circuitry to maintain stability under open input conditions. If the inputs are left open (pulled to V ) the Q outputs will go LOW. EE 8 8 The 100 Series contains temperature compensation. 1 1 Features SOIC8 TSSOP8 265 ps Propagation Delay D SUFFIX DT SUFFIX 5 ps Skew Between Outputs CASE 75107 CASE 948R02 PECL Mode Operating Range: V = 4.2 V to 5.7 with V = 0 V CC EE NECL Mode Operating Range: V = 0 V with V = 4.2 V to 5.7 V CC EE MARKING DIAGRAMS* Internal Input Pulldown Resistors These Devices are Pb-Free, Halogen Free and are RoHS Compliant 8 8 HEL11 HL11 ALYW ALYW Q 1 8 V 0 CC 1 1 8 8 Q 2 7 D 0 KEL11 KL11 ALYW ALYW 1 1 Q 3 6 D 1 H = MC10 L = Wafer Lot K = MC100 Y = Year 4Q = MC10 W = Work Week Q 4 5 V 1 EE 2E = MC100 M = Date Code A = Assembly Location = Pb-Free Package (Note: Microdot may be in either location) Figure 1. Logic Diagram and Pinout Assignment *For additional marking information, refer to Application Note AND8002/D. Table 1. PIN DESCRIPTION PIN FUNCTION D, D ECL Data Inputs ORDERING INFORMATION See detailed ordering and shipping information in the package Q0, Q0 Q1, Q1 ECL Data Outputs dimensions section on page 6 of this data sheet. V Positive Supply CC V Negative Supply EE Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 11 MC10EL11/DMC10EL11, MC100EL11 Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 K Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 1 KV Machine Model > 100 V Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8 Level 1 TSSOP8 Level 3 Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 44 Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit V PECL Mode Power Supply V = 0 V 8 V CC EE V NECL Mode Power Supply V = 0 V 8 V EE CC V PECL Mode Input Voltage V = 0 V V V 6 V I EE I CC NECL Mode Input Voltage V = 0 V V V 6 CC I EE I Output Current Continuous 50 mA out Surge 100 T Operating Temperature Range 40 to +85 C A T Storage Temperature Range 65 to +150 C stg Thermal Resistance (Junction-to-Ambient) 0 lfpm SOIC8 190 C/W JA 500 lfpm 130 Thermal Resistance (Junction-to-Case) Standard Board SOIC8 41 to 44 C/W JC Thermal Resistance (Junction-to-Ambient) 0 lfpm TSSOP8 185 C/W JA 500 lfpm 140 Thermal Resistance (Junction-to-Case) Standard Board TSSOP8 41 to 44 5% C/W JC T Wave Solder (Pb-Free) <2 to 3 sec 260C 265 C sol Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. JEDEC standard multilayer board 2S2P (2 signal, 2 power) www.onsemi.com 2