3.3 V/5 VECL Dual Differential Data and Clock D Flip-Flop With Set and Reset MC10EP29, MC100EP29 www.onsemi.com Description The MC10/100EP29 is a dual masterslave flipflop. The device MARKING DIAGRAM* features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW XXXX and transfers to the slave upon a positive transition on the clock input. EP29 The differential inputs have special circuitry which ensures device ALYW stability under open input conditions. When both differential inputs are left open the D input will pull down to V and the D input will TSSOP20 EE DT SUFFIX bias around V /2. The outputs will go to a defined state, however the CC CASE 948E state will be random based on how the flip flop powers up. 20 Both flip flops feature asynchronous, overriding Set and Reset 1 inputs. Note that the Set and Reset inputs cannot both be HIGH XXXX EP29 simultaneously. ALYW The V pin, an internally generated voltage supply, is available to BB this device only. For single-ended input conditions, the unused QFN20 MN SUFFIX differential input is connected to V as a switching reference voltage. BB CASE 485E V may also rebias AC coupled inputs. When used, decouple V BB BB and V via a 0.01 F capacitor and limit current sourcing or sinking CC to 0.5 mA. When not used, V should be left open. XXXX = MC10 or 100 BB A = Assembly Location The 100 Series contains temperature compensation. L = Wafer Lot Y = Year Features W = Work Week Maximum Frequency > 3 GHz Typical = PbFree Package 500 ps Typical Propagation Delays (Note: Microdot may be in either location) PECL Mode Operating Range: V = 3.0 V to 5.5 V CC *For additional marking information, refer to with V = 0 V EE Application Note AND8002/D. NECL Mode Operating Range: V = 0 V CC ORDERING INFORMATION with V = 3.0 V to 5.5 V EE Open Input Default State Package Device Shipping Safety Clamp on Inputs TSSOP20 75 Units / Tube MC10EP29DTG These are PbFree Devices (PbFree) TSSOP20 75 Units / Tube MC100EP29DTG (PbFree) TSSOP20 MC100EP29DTR2G 2500 / Tape & (PbFree) Reel QFN20 92 Units / Tube MC100EP29MNG (PbFree) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2014 1 Publication Order Number: April, 2021 Rev. 10 MC10EP29/DMC10EP29, MC100EP29 V R0 S0 Q0 Q0 Q1 Q1 S1 R1 V CC EE 20 19 18 17 16 15 14 13 12 11 R S Q Q S R Q Q CLK D D CLK 1 2354 678 9 10 D0 D0 V CLK0 CLK0 CLK1 CLK1 D1 D1 V BB CC Warning: All V and V pins must be externally connected CC EE to Power Supply to guarantee proper operation. Figure 1. 20 Lead Pinout (Top View) and Logic Diagram Exposed Pad D0 D0 V R0 S0 CC 20 19 18 17 16 1 15 V Q0 BB 2 14 CLK0 Q0 MC10/100EP29 3 13 CLK0 Q1 4 12 CLK1 Q1 5 11 CLK1 S1 67 8 9 10 D1 D1 V V R1 CC EE NOTE: The Exposed Pad (EP) on package bottom must be attached to a heatsinking conduit. The Exposed Pad may only be electrically connected to V . EE Figure 1. QFN20 Pinout (Top View) Table 1. PIN DESCRIPTION Pin Function Table 2. TRUTH TABLE D0*, D0* D1*, D1* ECL Differential Data Inputs R S D CLK Q Q R0*, R1* ECL Reset Inputs L L L Z L H CLK0*, CLK0* ECL Differential Clock Inputs L L H Z H L CLK1*, CLK1* ECL Differential Clock Inputs H L X X L H S0* S1* ECL Set Inputs L H X X H L Q0, Q0 Q1, Q1 ECL Differential Data Outputs H H X X Undef Undef V Reference Voltage Output BB Z = LOW to HIGH Transition X = Dont Care V Positive Supply CC V Negative Supply EE EP Exposed Pad *Pins will default LOW when left open. www.onsemi.com 2