MC10EP32, MC100EP32 3.3 V / 5 VECL 2 Divider Description The MC10/100EP32 is an integrated 2 divider with differential CLK inputs. The V pin, an internally generated voltage supply, is available to BB www.onsemi.com this device only. For single-ended input conditions, the unused differential input is connected to V as a switching reference voltage. BB V may also rebias AC coupled inputs. When used, decouple V BB BB 8 8 and V via a 0.01 F capacitor and limit current sourcing or sinking CC 1 to 0.5 mA. When not used, V should be left open. 1 BB The reset pin is asynchronous and is asserted on the rising edge. SOIC8NB TSSOP8 DFN8 Upon power-up, the internal flip-flops will attain a random state the D SUFFIX DT SUFFIX MN SUFFIX reset allows for the synchronization of multiple EP32s in a system. CASE CASE CASE 506AA 75107 948R02 The 100 Series contains temperature compensation. Features 350 ps Typical Propagation Delay MARKING DIAGRAMS* Maximum Frequency > 4 GHz Typical (Figure 3) 8 8 PECL Mode Operating Range: HEP32 V = 3.0 V to 5.5 V with V = 0 V HP32 CC EE ALYW ALYW NECL Mode Operating Range: 14 1 V = 0 V with V = 3.0 V to 5.5 V 1 CC EE Open Input Default State 8 8 Safety Clamp on Inputs KEP32 KP32 Q Output Will Default LOW with Inputs Open or at V EE ALYW ALYW These Devices are Pb-Free, Halogen Free and are RoHS Compliant 14 1 1 H = MC10 A = Assembly Location K = MC100 L = Wafer Lot 5P = MC10 Y = Year 3K = MC100 W = Work Week M = Date Code = Pb-Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: July, 2016 Rev. 12 MC10EP32/D 5P M 3K M MC10EP32, MC100EP32 Table 1. PIN DESCRIPTION RESET 1 8 V CC Pin Function R CLK, CLK* ECL Clock Inputs Reset* ECL Asynchronous Reset CLK 2 7 Q V Reference Voltage Output BB 2 Q, Q ECL Data Outputs V Positive Supply CLK 3 6 Q CC V Negative Supply EE EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal V45 V BB EE conduit. Electrically connect to the most negative supply (GND) or leave uncon- nected, floating open. Figure 1. 8-Lead Pinout (Top View) and Logic *Pins will default LOW when left open. Diagram Table 2. TRUTH TABLE CLK CLK RESET Q Q X X Z L H Z Z L F F Z = LOW to HIGH Transition Z = HIGH to LOW Transition F = Divide by 2 Function CLK t RR RESET Q Figure 2. Timing Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor N/A ESD Protection Human Body Model > 4 kV Machine Model > 200 V Charged Device Model > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg SOIC8NB Level 1 TSSOP8 Level 3 DFN8 Level 1 Flammability Rating UL 94 V0 0.125 in Oxygen Index: 28 to 34 Transistor Count 78 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. www.onsemi.com 2