MC10EP33, MC100EP33
3.3V/5VECL 4 Divider
Description
The MC10/100EP33 is an integrated 4 divider. The differential
clock inputs.
The V pin, an internally generated voltage supply, is available to
BB
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this device only. For single-ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
V may also rebias AC coupled inputs. When used, decouple V
BB BB
and V via a 0.01 F capacitor and limit current sourcing or sinking
CC
8 8
to 0.5 mA. When not used, V should be left open.
BB
1
1
The reset pin is asynchronous and is asserted on the rising edge.
Upon powerup, the internal flip-flops will attain a random state; the
SOIC8 NB TSSOP8 DFN8
reset allows for the synchronization of multiple EP33s in a system.
D SUFFIX DT SUFFIX MN SUFFIX
The 100 Series contains temperature compensation.
CASE 75107 CASE 948R02 CASE 506AA
Features
320 ps Propagation Delay
MARKING DIAGRAMS*
Maximum Frequency = > 4 GHz Typical
PECL Mode Operating Range:
8
8
V = 3.0 V to 5.5 V with V = 0 V
CC EE
HEP64
HP64
ALYW
NECL Mode Operating Range:
ALYW
V = 0 V with V = 3.0 V to 5.5 V
14
CC EE
1
1
Open Input Default State
8 8
Safety Clamp on Inputs
KEP64
Q Output Will Default LOW with Inputs Open or at V
EE KP64
ALYW
ALYW
V Output
BB
14
1
1
These Devices are Pb-Free, Halogen Free and are RoHS Compliant
SOIC8 NB TSSOP8 DFN8
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5Q = MC10 Y = Year
3L = MC100 W = Work Week
M = Date Code
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
Semiconductor Components Industries, LLC, 2016
1 Publication Order Number:
August, 2016 Rev. 11 MC10EP33/D
3L M 5Q M
MC10EP33, MC100EP33
Table 1. PIN DESCRIPTION
PIN FUNCTION
RESET 1 8 V CLK*, CLK* ECL Clock Inputs
CC
R
Reset* ECL Asynchronous Reset
V Reference Voltage Output
BB
CLK 2 7 Q
Q, Q ECL Data Outputs
4 V Positive Supply
CC
V Negative Supply
EE
CLK 3 6 Q
EP (DFN8 only) Thermal exposed pad must
be connected to a sufficient thermal con-
duit. Electrically connect to the most neg-
ative supply (GND) or leave unconnected,
V45 V
BB EE
floating open.
* Pins will default LOW when left open.
Table 2. TRUTH TABLE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
CLK CLK RESET Q Q
X X Z L H
Z Z L F F
Z = LOW to HIGH Transition
Z = HIGH to LOW Transition
F = Divide by 4 Function
CLK
t
RR
RESET
Q
Figure 2. Timing Diagram
Table 3. ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 k
Internal Input Pullup Resistor NA
ESD Protection
Human Body Model
> 4 kV
Machine Model
> 200 V
Charged Device Model
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Pb-Free Pkg
SOIC8 NB Level 1
TSSOP8 Level 3
DFN8 Level 1
Flammability Rating Oxygen Index: 28 to 34 UL94 V0 @ 0.125 in
Transistor Count 91 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2